Skip to content

Commit b042887

Browse files
mbrkusaninmbrkusanin
authored
[AMDGPU] Rename TH_STORE_RT_WB to TH_STORE_WB (#135171)
So it matches the documentation Fixes: SWDEV-526726
1 parent 4244a91 commit b042887

File tree

9 files changed

+12
-12
lines changed

9 files changed

+12
-12
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6776,7 +6776,7 @@ ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
67766776

67776777
if (Value == "TH_DEFAULT")
67786778
TH = AMDGPU::CPol::TH_RT;
6779-
else if (Value == "TH_STORE_LU" || Value == "TH_LOAD_RT_WB" ||
6779+
else if (Value == "TH_STORE_LU" || Value == "TH_LOAD_WB" ||
67806780
Value == "TH_LOAD_NT_WB") {
67816781
return Error(StringLoc, "invalid th value");
67826782
} else if (Value.consume_front("TH_ATOMIC_")) {
@@ -6811,7 +6811,7 @@ ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
68116811
.Case("NT", AMDGPU::CPol::TH_NT)
68126812
.Case("HT", AMDGPU::CPol::TH_HT)
68136813
.Case("LU", AMDGPU::CPol::TH_LU)
6814-
.Case("RT_WB", AMDGPU::CPol::TH_RT_WB)
6814+
.Case("WB", AMDGPU::CPol::TH_WB)
68156815
.Case("NT_RT", AMDGPU::CPol::TH_NT_RT)
68166816
.Case("RT_NT", AMDGPU::CPol::TH_RT_NT)
68176817
.Case("NT_HT", AMDGPU::CPol::TH_NT_HT)

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -206,9 +206,9 @@ void AMDGPUInstPrinter::printTH(const MCInst *MI, int64_t TH, int64_t Scope,
206206
case AMDGPU::CPol::TH_HT:
207207
O << "HT";
208208
break;
209-
case AMDGPU::CPol::TH_BYPASS: // or LU or RT_WB
209+
case AMDGPU::CPol::TH_BYPASS: // or LU or WB
210210
O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS"
211-
: (IsStore ? "RT_WB" : "LU"));
211+
: (IsStore ? "WB" : "LU"));
212212
break;
213213
case AMDGPU::CPol::TH_NT_RT:
214214
O << "NT_RT";

‎llvm/lib/Target/AMDGPU/SIDefines.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -396,7 +396,7 @@ enum CPol {
396396
TH_NT = 1, // non-temporal
397397
TH_HT = 2, // high-temporal
398398
TH_LU = 3, // last use
399-
TH_RT_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
399+
TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
400400
TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
401401
TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
402402
TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1097,7 +1097,7 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
10971097
;
10981098
; GFX12-LABEL: store_1d_glc_slc:
10991099
; GFX12: ; %bb.0: ; %main_body
1100-
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB a16
1100+
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16
11011101
; GFX12-NEXT: s_endpgm
11021102
main_body:
11031103
%s = extractelement <2 x i16> %coords, i32 0

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1354,7 +1354,7 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
13541354
;
13551355
; GFX12-LABEL: store_1d_glc_slc:
13561356
; GFX12: ; %bb.0: ; %main_body
1357-
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x30,0x00,0x04,0x00,0x00,0x00]
1357+
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB a16 ; encoding: [0x40,0x80,0xc1,0xd3,0x00,0x00,0x30,0x00,0x04,0x00,0x00,0x00]
13581358
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
13591359
main_body:
13601360
%s = extractelement <2 x i16> %coords, i32 0

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3837,7 +3837,7 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat
38373837
;
38383838
; GFX12-LABEL: store_1d_glc_slc:
38393839
; GFX12: ; %bb.0: ; %main_body
3840-
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB
3840+
; GFX12-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_STORE_WB
38413841
; GFX12-NEXT: s_endpgm
38423842
main_body:
38433843
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)

‎llvm/test/MC/AMDGPU/gfx12_asm_vimage.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -393,7 +393,7 @@ image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
393393
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_HT
394394
// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
395395

396-
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB
396+
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB
397397
// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
398398

399399
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_RT

‎llvm/test/MC/AMDGPU/gfx12_err.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,13 +82,13 @@ image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT
8282
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_LU
8383
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid th value
8484

85-
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_RT_WB
85+
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_WB
8686
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid th value
8787

8888
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_NT_WB
8989
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid th value
9090

91-
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB scope:SCOPE_SYS
91+
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB scope:SCOPE_SYS
9292
// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: scope and th combination is not valid
9393

9494
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_BYPASS scope:SCOPE_DEV

‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -394,7 +394,7 @@
394394
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_HT ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00]
395395
0x00,0x80,0x41,0xd0,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00
396396

397-
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_RT_WB ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
397+
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_WB ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00]
398398
0x00,0x80,0x41,0xd0,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00
399399

400400
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_NT_RT ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00]

0 commit comments

Comments
 (0)