Regression fix: store impl class as member

Author: optimisan

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -98,6 +98,10 @@
 #include <vector>
 
 namespace llvm {
+namespace impl_detail {
+class MachineSchedulerImpl;
+class PostMachineSchedulerImpl;
+} // namespace impl_detail
 
 namespace MISched {
 enum Direction {
@@ -1386,20 +1390,26 @@ createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
                                const TargetRegisterInfo *TRI);
 
 class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
+  std::unique_ptr<impl_detail::MachineSchedulerImpl> Impl;
   const TargetMachine *TM;
 
 public:
-  MachineSchedulerPass(const TargetMachine *TM) : TM(TM) {}
+  MachineSchedulerPass(const TargetMachine *TM);
+  MachineSchedulerPass(MachineSchedulerPass &&Other);
+  ~MachineSchedulerPass();
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
 };
 
 class PostMachineSchedulerPass
     : public PassInfoMixin<PostMachineSchedulerPass> {
+  std::unique_ptr<impl_detail::PostMachineSchedulerImpl> Impl;
   const TargetMachine *TM;
 
 public:
-  PostMachineSchedulerPass(const TargetMachine *TM) : TM(TM) {}
+  PostMachineSchedulerPass(const TargetMachine *TM);
+  PostMachineSchedulerPass(PostMachineSchedulerPass &&Other);
+  ~PostMachineSchedulerPass();
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
 };

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -214,7 +214,8 @@ MachineSchedContext::~MachineSchedContext() {
   delete RegClassInfo;
 }
 
-namespace {
+namespace llvm {
+namespace impl_detail {
 
 /// Base class for the machine scheduler classes.
 class MachineSchedulerBase : public MachineSchedContext {
@@ -224,38 +225,67 @@ class MachineSchedulerBase : public MachineSchedContext {
 
 /// Impl class for MachineScheduler.
 class MachineSchedulerImpl : public MachineSchedulerBase {
+  // These are only for using MF.verify()
+  // remove when verify supports passing in all analyses
   MachineFunctionPass *P = nullptr;
   MachineFunctionAnalysisManager *MFAM = nullptr;
 
 public:
-  MachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P);
-  MachineSchedulerImpl(MachineFunction &Func,
-                       MachineFunctionAnalysisManager &MFAM,
-                       const TargetMachine *TargetM);
-  bool run();
+  struct RequiredAnalyses {
+    MachineLoopInfo &MLI;
+    MachineDominatorTree &MDT;
+    AAResults &AA;
+    LiveIntervals &LIS;
+  };
+
+  MachineSchedulerImpl() {}
+  // Migration only
+  void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+  void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
+
+  bool run(MachineFunction &MF, const TargetMachine &TM,
+           const RequiredAnalyses &Analyses);
 
 protected:
   ScheduleDAGInstrs *createMachineScheduler();
 };
 
 /// Impl class for PostMachineScheduler.
 class PostMachineSchedulerImpl : public MachineSchedulerBase {
+  // These are only for using MF.verify()
+  // remove when verify supports passing in all analyses
   MachineFunctionPass *P = nullptr;
   MachineFunctionAnalysisManager *MFAM = nullptr;
 
 public:
-  PostMachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P);
-  PostMachineSchedulerImpl(MachineFunction &Func,
-                           MachineFunctionAnalysisManager &MFAM,
-                           const TargetMachine *TargetM);
-  bool run();
+  struct RequiredAnalyses {
+    MachineLoopInfo &MLI;
+    AAResults &AA;
+  };
+  PostMachineSchedulerImpl() {}
+  // Migration only
+  void setLegacyPass(MachineFunctionPass *P) { this->P = P; }
+  void setMFAM(MachineFunctionAnalysisManager *MFAM) { this->MFAM = MFAM; }
+
+  bool run(MachineFunction &Func, const TargetMachine &TM,
+           const RequiredAnalyses &Analyses);
 
 protected:
   ScheduleDAGInstrs *createPostMachineScheduler();
 };
 
+} // namespace impl_detail
+} // namespace llvm
+
+using impl_detail::MachineSchedulerBase;
+using impl_detail::MachineSchedulerImpl;
+using impl_detail::PostMachineSchedulerImpl;
+
+namespace {
 /// MachineScheduler runs after coalescing and before register allocation.
 class MachineSchedulerLegacy : public MachineFunctionPass {
+  MachineSchedulerImpl Impl;
+
 public:
   MachineSchedulerLegacy();
   void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -266,10 +296,12 @@ class MachineSchedulerLegacy : public MachineFunctionPass {
 
 /// PostMachineScheduler runs after shortly before code emission.
 class PostMachineSchedulerLegacy : public MachineFunctionPass {
+  PostMachineSchedulerImpl Impl;
+
 public:
   PostMachineSchedulerLegacy();
   void getAnalysisUsage(AnalysisUsage &AU) const override;
-  bool runOnMachineFunction(MachineFunction&) override;
+  bool runOnMachineFunction(MachineFunction &) override;
 
   static char ID; // Class identification, replacement for typeinfo
 };
@@ -403,31 +435,6 @@ nextIfDebug(MachineBasicBlock::iterator I,
       .getNonConstIterator();
 }
 
-MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
-                                           MachineFunctionPass *P)
-    : P(P) {
-  MF = &Func;
-  MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
-  MDT = &P->getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
-  TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-  AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
-  LIS = &P->getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-}
-
-MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
-                                           MachineFunctionAnalysisManager &MFAM,
-                                           const TargetMachine *TargetM)
-    : MFAM(&MFAM) {
-  MF = &Func;
-  TM = TargetM;
-  MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
-  MDT = &MFAM.getResult<MachineDominatorTreeAnalysis>(Func);
-  auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
-                  .getManager();
-  AA = &FAM.getResult<AAManager>(Func.getFunction());
-  LIS = &MFAM.getResult<LiveIntervalsAnalysis>(Func);
-}
-
 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
 ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
   // Select the scheduler, or set the default.
@@ -444,7 +451,15 @@ ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
   return createGenericSchedLive(this);
 }
 
-bool MachineSchedulerImpl::run() {
+bool MachineSchedulerImpl::run(MachineFunction &Func, const TargetMachine &TM,
+                               const RequiredAnalyses &Analyses) {
+  MF = &Func;
+  MLI = &Analyses.MLI;
+  MDT = &Analyses.MDT;
+  this->TM = &TM;
+  AA = &Analyses.AA;
+  LIS = &Analyses.LIS;
+
   if (VerifyScheduling) {
     LLVM_DEBUG(LIS->dump());
     const char *MSchedBanner = "Before machine scheduling.";
@@ -471,27 +486,6 @@ bool MachineSchedulerImpl::run() {
   return true;
 }
 
-PostMachineSchedulerImpl::PostMachineSchedulerImpl(MachineFunction &Func,
-                                                   MachineFunctionPass *P)
-    : P(P) {
-  MF = &Func;
-  MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
-  TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-  AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
-}
-
-PostMachineSchedulerImpl::PostMachineSchedulerImpl(
-    MachineFunction &Func, MachineFunctionAnalysisManager &MFAM,
-    const TargetMachine *TargetM)
-    : MFAM(&MFAM) {
-  MF = &Func;
-  TM = TargetM;
-  MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
-  auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
-                  .getManager();
-  AA = &FAM.getResult<AAManager>(Func.getFunction());
-}
-
 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
 /// the caller. We don't have a command line option to override the postRA
 /// scheduler. The Target must configure it.
@@ -505,7 +499,14 @@ ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
   return createGenericSchedPostRA(this);
 }
 
-bool PostMachineSchedulerImpl::run() {
+bool PostMachineSchedulerImpl::run(MachineFunction &Func,
+                                   const TargetMachine &TM,
+                                   const RequiredAnalyses &Analyses) {
+  MF = &Func;
+  MLI = &Analyses.MLI;
+  this->TM = &TM;
+  AA = &Analyses.AA;
+
   if (VerifyScheduling) {
     const char *PostMSchedBanner = "Before post machine scheduling.";
     if (P)
@@ -558,10 +559,27 @@ bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
 
   LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
 
-  MachineSchedulerImpl Impl(MF, this);
-  return Impl.run();
+  auto &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+  auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+  auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
+  auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+  Impl.setLegacyPass(this);
+  return Impl.run(MF, TM, {MLI, MDT, AA, LIS});
 }
 
+MachineSchedulerPass::MachineSchedulerPass(const TargetMachine *TM)
+    : Impl(std::make_unique<MachineSchedulerImpl>()), TM(TM) {}
+MachineSchedulerPass::~MachineSchedulerPass() = default;
+MachineSchedulerPass::MachineSchedulerPass(MachineSchedulerPass &&Other) =
+    default;
+
+PostMachineSchedulerPass::PostMachineSchedulerPass(const TargetMachine *TM)
+    : Impl(std::make_unique<PostMachineSchedulerImpl>()), TM(TM) {}
+PostMachineSchedulerPass::PostMachineSchedulerPass(
+    PostMachineSchedulerPass &&Other) = default;
+PostMachineSchedulerPass::~PostMachineSchedulerPass() = default;
+
 PreservedAnalyses
 MachineSchedulerPass::run(MachineFunction &MF,
                           MachineFunctionAnalysisManager &MFAM) {
@@ -573,9 +591,14 @@ MachineSchedulerPass::run(MachineFunction &MF,
   }
 
   LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
-
-  MachineSchedulerImpl Impl(MF, MFAM, TM);
-  bool Changed = Impl.run();
+  auto &MLI = MFAM.getResult<MachineLoopAnalysis>(MF);
+  auto &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+  auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+                  .getManager();
+  auto &AA = FAM.getResult<AAManager>(MF.getFunction());
+  auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+  Impl->setMFAM(&MFAM);
+  bool Changed = Impl->run(MF, *TM, {MLI, MDT, AA, LIS});
   if (!Changed)
     return PreservedAnalyses::all();
 
@@ -598,9 +621,11 @@ bool PostMachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
     return false;
   }
   LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs()));
-
-  PostMachineSchedulerImpl Impl(MF, this);
-  return Impl.run();
+  auto &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+  auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
+  Impl.setLegacyPass(this);
+  return Impl.run(MF, TM, {MLI, AA});
 }
 
 PreservedAnalyses
@@ -614,9 +639,13 @@ PostMachineSchedulerPass::run(MachineFunction &MF,
     return PreservedAnalyses::all();
   }
   LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs()));
+  auto &MLI = MFAM.getResult<MachineLoopAnalysis>(MF);
+  auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+                  .getManager();
+  auto &AA = FAM.getResult<AAManager>(MF.getFunction());
 
-  PostMachineSchedulerImpl Impl(MF, MFAM, TM);
-  bool Changed = Impl.run();
+  Impl->setMFAM(&MFAM);
+  bool Changed = Impl->run(MF, *TM, {MLI, AA});
   if (!Changed)
     return PreservedAnalyses::all();