[DAGCombine] Correctly extend the constant RHS

Author: dtcxzyw

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -5125,10 +5125,11 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
           !ISD::isUnsignedIntSetCC(Cond))) &&
         isTypeDesirableForOp(ISD::SETCC, N0.getOperand(0).getValueType())) {
       EVT NewVT = N0.getOperand(0).getValueType();
-      SDValue NewConst = DAG.getConstant(ISD::isSignedIntSetCC(Cond)
-                                             ? C1.sext(NewVT.getSizeInBits())
-                                             : C1.zext(NewVT.getSizeInBits()),
-                                         dl, NewVT);
+      SDValue NewConst = DAG.getConstant(
+          (N0->getFlags().hasNoSignedWrap() && !ISD::isUnsignedIntSetCC(Cond))
+              ? C1.sext(NewVT.getSizeInBits())
+              : C1.zext(NewVT.getSizeInBits()),
+          dl, NewVT);
       return DAG.getSetCC(dl, VT, N0.getOperand(0), NewConst, Cond);
     }
 

llvm/test/CodeGen/X86/pr152630.ll

@@ -6,7 +6,7 @@ define i32 @pr152630(i1 %cond) nounwind {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andl $1, %edi
 ; CHECK-NEXT:    decl %edi
-; CHECK-NEXT:    cmpl $255, %edi
+; CHECK-NEXT:    cmpl $-1, %edi
 ; CHECK-NEXT:    je .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    movzbl %dil, %eax