[RISCV] Add assembler support for Zvma

Author: FantasqueX

clang/test/Driver/print-supported-extensions-riscv.c

@@ -192,6 +192,7 @@
 // CHECK-NEXT:     zalasr               0.1       'Zalasr' (Load-Acquire and Store-Release Instructions)
 // CHECK-NEXT:     zvbc32e              0.7       'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
 // CHECK-NEXT:     zvkgs                0.7       'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
+// CHECK-NEXT:     zvma                 0.0       'Zvma' (High-throughput Matrix-multiplication Computation)
 // CHECK-NEXT:     zvqdotq              0.0       'Zvqdotq' (Vector quad widening 4D Dot Product)
 // CHECK-NEXT:     smctr                1.0       'Smctr' (Control Transfer Records Machine Level)
 // CHECK-NEXT:     ssctr                1.0       'Ssctr' (Control Transfer Records Supervisor Level)

clang/test/Preprocessor/riscv-target-features.c

@@ -203,6 +203,7 @@
 // CHECK-NOT: __riscv_zvfbfwma {{.*$}}
 // CHECK-NOT: __riscv_zvkgs {{.*$}}
 // CHECK-NOT: __riscv_zvqdotq {{.*$}}
+// CHECK-NOT: __riscv_zvma {{.*$}}
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ia -E -dM %s \
@@ -1770,6 +1771,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZVQDOTQ-EXT %s
 // CHECK-ZVQDOTQ-EXT: __riscv_zvqdotq 0{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_zve32x_zvma0p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVMA-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN:   -march=rv64i_zve32x_zvma0p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-ZVMA-EXT %s
+// CHECK-ZVMA-EXT: __riscv_zvma 0111{{$}}
+
 // RUN: %clang -target riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32izicfiss1p0 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s

llvm/docs/RISCVUsage.rst

@@ -340,6 +340,9 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-zvqdotq``
   LLVM implements the `0.0.1 draft specification <https://github.com/riscv/riscv-dot-product/releases/tag/v0.0.1>`__.
 
+``experimental-zvma``
+  LLVM implements the `SiFive proposal specification <https://lists.riscv.org/g/tech-attached-matrix-extension/topic/sifive_proposal_for_risc_v/110189555>`__.
+
 To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using.  To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`.  Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
 
 Vendor Extensions

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -830,6 +830,15 @@ def HasStdExtZvqdotq : Predicate<"Subtarget->hasStdExtZvqdotq()">,
                        AssemblerPredicate<(all_of FeatureStdExtZvqdotq),
                            "'Zvqdotq' (Vector quad widening 4D Dot Product)">;
 
+// High-throughput Matrix-multiplication Computation
+
+def FeatureStdExtZvma
+    : RISCVExperimentalExtension<0, 0, "High-throughput Matrix-multiplication Computation",
+                                 [FeatureStdExtZve32x]>;
+def HasStdExtZvma : Predicate<"Subtarget->hasStdExtZvma()">,
+                    AssemblerPredicate<(all_of FeatureStdExtZvma),
+                        "'Zvma' (High-throughput Matrix-multiplication Computation)">;
+
 // Vector instruction predicates
 
 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2139,6 +2139,7 @@ include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZvk.td"
 include "RISCVInstrInfoZvqdotq.td"
+include "RISCVInstrInfoZvma.td"
 
 // Integer
 include "RISCVInstrInfoZimop.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZvma.td

@@ -0,0 +1,21 @@
+class VSetT<bits<5> func5, dag outs, dag ins, string opcodestr, string argstr>
+  : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31}    = 1;
+  let Inst{30-25} = 0b000010;
+  let Inst{24-20} = func5;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b111;
+  let Inst{11-7}  = rd;
+  let Inst{6-0}   = 0x57;
+}
+
+let Predicates = [HasStdExtZvma] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+  def VSETTN : VSetT<0b00000, (outs GPR:$rd), (ins GPR:$rs1), "vsettn", "$rd, %rs1">;
+  def VSETTM : VSetT<0b00001, (outs GPR:$rd), (ins GPR:$rs1), "vsettm", "$rd, %rs1">;
+  def VSETTK : VSetT<0b00010, (outs GPR:$rd), (ins GPR:$rs1), "vsettk", "$rd, %rs1">;
+} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
+} // Predicates = [HasStdExtZvma]