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1 parent f75fe90 commit b0d476eCopy full SHA for b0d476e
mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
@@ -83,6 +83,7 @@ func.func @broadcast_single_elem_vec1d_from_f32(%arg0: f32) -> vector<1xf32> {
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// CHECK-LABEL: @broadcast_single_elem_vec1d_from_f32
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// CHECK-SAME: %[[A:.*]]: f32)
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// CHECK: %[[T0:.*]] = llvm.insertelement %[[A]]
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+// CHECK-NOT: llvm.shufflevector
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// CHECK: return %[[T0]] : vector<1xf32>
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// -----
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