[RISCV] Use opaque pointers in some tests. NFC (#127906)

Author: topperc

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

@@ -34,7 +34,7 @@ declare { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv1i64(
   iXLen,
   iXLen);
 
-define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(ptr %0, <vscale x 1 x i1> %1, iXLen %2, iXLen* %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(ptr %0, <vscale x 1 x i1> %1, iXLen %2, ptr %3) nounwind {
 ; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
@@ -58,7 +58,7 @@ entry:
     iXLen %2, iXLen 3)
   %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 0
   %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 1
-  store iXLen %c, iXLen* %3
+  store iXLen %c, ptr %3
 
   ret <vscale x 1 x i64> %b
 }

llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll

@@ -32,7 +32,7 @@ declare { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv1i64(
   <vscale x 1 x i1>,
   iXLen,
   iXLen)
-define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, iXLen* %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {
 ; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
@@ -56,7 +56,7 @@ entry:
     iXLen %3, iXLen 1)
   %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 0
   %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 1
-  store iXLen %c, iXLen* %4
+  store iXLen %c, ptr %4
 
   ret <vscale x 1 x i64> %b
 }

llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll

@@ -32,7 +32,7 @@ declare { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv1i64(
   <vscale x 1 x i1>,
   iXLen,
   iXLen)
-define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, iXLen* %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {
 ; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    vsetvli zero, a1, e64, m1, tu, ma
@@ -56,7 +56,7 @@ entry:
     iXLen %3, iXLen 2)
   %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 0
   %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 1
-  store iXLen %c, iXLen* %4
+  store iXLen %c, ptr %4
 
   ret <vscale x 1 x i64> %b
 }

llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll

@@ -32,7 +32,7 @@ declare { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv1i64(
   <vscale x 1 x i1>,
   iXLen,
   iXLen)
-define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, iXLen* %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {
 ; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    vsetvli zero, a1, e64, m1, tu, mu
@@ -56,7 +56,7 @@ entry:
     iXLen %3, iXLen 0)
   %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 0
   %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 1
-  store iXLen %c, iXLen* %4
+  store iXLen %c, ptr %4
 
   ret <vscale x 1 x i64> %b
 }

llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll

@@ -52,7 +52,7 @@ declare { <vscale x 1 x i8>, iXLen } @llvm.riscv.vleff(
   ptr,
   iXLen);
 
-define <vscale x 1 x i8> @intrinsic_vleff_v_tu(<vscale x 1 x i8> %0, ptr %1, iXLen %2, iXLen* %3) nounwind {
+define <vscale x 1 x i8> @intrinsic_vleff_v_tu(<vscale x 1 x i8> %0, ptr %1, iXLen %2, ptr %3) nounwind {
 ; RV32-LABEL: intrinsic_vleff_v_tu:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    vsetvli zero, a1, e8, mf8, tu, ma
@@ -75,7 +75,7 @@ entry:
     iXLen %2)
   %b = extractvalue { <vscale x 1 x i8>, iXLen } %a, 0
   %c = extractvalue { <vscale x 1 x i8>, iXLen } %a, 1
-  store iXLen %c, iXLen* %3
+  store iXLen %c, ptr %3
   ret <vscale x 1 x i8> %b
 }