|
54 | 54 | define amdgpu_gs void @mask_hazard_valu_vcmp_sgpr() { ret void } |
55 | 55 | define amdgpu_gs void @mask_hazard_combine1() { ret void } |
56 | 56 | define amdgpu_gs void @mask_hazard_combine2() { ret void } |
| 57 | + define amdgpu_gs void @mask_hazard_combine3() { ret void } |
| 58 | + define amdgpu_gs void @mask_hazard_combine4() { ret void } |
| 59 | + define amdgpu_gs void @mask_hazard_combine5() { ret void } |
57 | 60 | ... |
58 | 61 |
|
59 | 62 | --- |
@@ -1041,3 +1044,108 @@ body: | |
1041 | 1044 | $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $vgpr5, implicit $exec |
1042 | 1045 | S_ENDPGM 0 |
1043 | 1046 | ... |
| 1047 | + |
| 1048 | +--- |
| 1049 | +name: mask_hazard_combine3 |
| 1050 | +body: | |
| 1051 | + bb.0: |
| 1052 | + ; GFX11-LABEL: name: mask_hazard_combine3 |
| 1053 | + ; GFX11: $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1054 | + ; GFX11-NEXT: $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1055 | + ; GFX11-NEXT: $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1056 | + ; GFX11-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1057 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 65533 |
| 1058 | + ; GFX11-NEXT: $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1059 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951 |
| 1060 | + ; GFX11-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1061 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951 |
| 1062 | + ; GFX11-NEXT: S_ENDPGM 0 |
| 1063 | + ; |
| 1064 | + ; GFX12-LABEL: name: mask_hazard_combine3 |
| 1065 | + ; GFX12: $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1066 | + ; GFX12-NEXT: $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1067 | + ; GFX12-NEXT: $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1068 | + ; GFX12-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1069 | + ; GFX12-NEXT: $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1070 | + ; GFX12-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1071 | + ; GFX12-NEXT: S_ENDPGM 0 |
| 1072 | + $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1073 | + $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1074 | + $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1075 | + V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1076 | + $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1077 | + $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1078 | + S_ENDPGM 0 |
| 1079 | +... |
| 1080 | + |
| 1081 | +--- |
| 1082 | +name: mask_hazard_combine4 |
| 1083 | +body: | |
| 1084 | + bb.0: |
| 1085 | + ; GFX11-LABEL: name: mask_hazard_combine4 |
| 1086 | + ; GFX11: $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1087 | + ; GFX11-NEXT: $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1088 | + ; GFX11-NEXT: $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1089 | + ; GFX11-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1090 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 65533 |
| 1091 | + ; GFX11-NEXT: $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1092 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951 |
| 1093 | + ; GFX11-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $vcc |
| 1094 | + ; GFX11-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1095 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951 |
| 1096 | + ; GFX11-NEXT: S_ENDPGM 0 |
| 1097 | + ; |
| 1098 | + ; GFX12-LABEL: name: mask_hazard_combine4 |
| 1099 | + ; GFX12: $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1100 | + ; GFX12-NEXT: $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1101 | + ; GFX12-NEXT: $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1102 | + ; GFX12-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1103 | + ; GFX12-NEXT: $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1104 | + ; GFX12-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $vcc |
| 1105 | + ; GFX12-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1106 | + ; GFX12-NEXT: S_ENDPGM 0 |
| 1107 | + $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1108 | + $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1109 | + $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1110 | + V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1111 | + $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1112 | + $sgpr4_sgpr5 = S_MOV_B64 $vcc |
| 1113 | + $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1114 | + S_ENDPGM 0 |
| 1115 | +... |
| 1116 | + |
| 1117 | +--- |
| 1118 | +name: mask_hazard_combine5 |
| 1119 | +body: | |
| 1120 | + bb.0: |
| 1121 | + ; GFX11-LABEL: name: mask_hazard_combine5 |
| 1122 | + ; GFX11: $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1123 | + ; GFX11-NEXT: $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1124 | + ; GFX11-NEXT: $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1125 | + ; GFX11-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1126 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 65533 |
| 1127 | + ; GFX11-NEXT: $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1128 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951 |
| 1129 | + ; GFX11-NEXT: $sgpr5 = S_MOV_B32 $sgpr1 |
| 1130 | + ; GFX11-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1131 | + ; GFX11-NEXT: S_WAITCNT_DEPCTR 61951 |
| 1132 | + ; GFX11-NEXT: S_ENDPGM 0 |
| 1133 | + ; |
| 1134 | + ; GFX12-LABEL: name: mask_hazard_combine5 |
| 1135 | + ; GFX12: $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1136 | + ; GFX12-NEXT: $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1137 | + ; GFX12-NEXT: $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1138 | + ; GFX12-NEXT: V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1139 | + ; GFX12-NEXT: $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1140 | + ; GFX12-NEXT: $sgpr5 = S_MOV_B32 $sgpr1 |
| 1141 | + ; GFX12-NEXT: $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1142 | + ; GFX12-NEXT: S_ENDPGM 0 |
| 1143 | + $vgpr3 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $vcc, implicit $exec |
| 1144 | + $vgpr4 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0_sgpr1, implicit $exec |
| 1145 | + $vgpr5 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, implicit $exec |
| 1146 | + V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec |
| 1147 | + $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 2, $sgpr10, implicit $exec |
| 1148 | + $sgpr5 = S_MOV_B32 $sgpr1 |
| 1149 | + $sgpr2_sgpr3 = V_CMP_EQ_U32_e64 3, $sgpr10, implicit $exec |
| 1150 | + S_ENDPGM 0 |
| 1151 | +... |
0 commit comments