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1 parent 24aa2e7 commit b136481Copy full SHA for b136481
mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -675,7 +675,7 @@ class ROCDL_TrLoadOp<ROCDL_TrLoadOpMeta meta> :
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dag args = (ins Arg<LLVM_PointerInAddressSpace<meta.addrKind.space>, "", [MemRead]>:$ptr);
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let arguments = !con(args, baseArgs);
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- let summary = "Loads and transposes a matrix from " # meta.addrKind.name # " memory or ds to registers (available in gfx1250+).";
+ let summary = "Loads and transposes a matrix from " # meta.addrKind.name # " memory to registers (available in gfx1250+).";
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let description = [{
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Load a matrix of }] # meta.inBits # [{-bit data from the }] # meta.addrKind.name # [{ memory,
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transpose data between row-major and column-major order,
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