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[SCEV] Add poison check.
1 parent 137ff32 commit b16665e

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9 files changed

+60
-53
lines changed

9 files changed

+60
-53
lines changed

‎llvm/lib/Analysis/ScalarEvolution.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5927,7 +5927,8 @@ const SCEV *ScalarEvolution::createAddRecFromPHI(PHINode *PN) {
59275927
// PHI(f(0), f({1,+,1})) --> f({0,+,1})
59285928

59295929
// Do not allow refinement in rewriting of BEValue.
5930-
if (isGuaranteedNotToCauseUB(BEValue)) {
5930+
if (isGuaranteedNotToCauseUB(BEValue) &&
5931+
isGuaranteedNotToBePoison(BEValue)) {
59315932
const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this);
59325933
const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false);
59335934
if (Shifted != getCouldNotCompute() && Start != getCouldNotCompute()) {

‎llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; PR79137: If the noalias.scope.decl is located inside the loop, we cannot
55
; assume that the accesses don't alias across iterations.
66

7-
define void @test_scope_in_loop(ptr %arg, i64 %num) {
7+
define void @test_scope_in_loop(ptr noundef %arg, i64 %num) {
88
; CHECK-LABEL: 'test_scope_in_loop'
99
; CHECK-NEXT: loop:
1010
; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
33

4-
define void @arm_cmplx_dot_prod_f32(ptr %pSrcA, ptr %pSrcB, i32 %numSamples, ptr nocapture %realResult, ptr nocapture %imagResult) {
4+
define void @arm_cmplx_dot_prod_f32(ptr noundef %pSrcA, ptr noundef %pSrcB, i32 %numSamples, ptr nocapture %realResult, ptr nocapture %imagResult) {
55
; CHECK-LABEL: arm_cmplx_dot_prod_f32:
66
; CHECK: @ %bb.0: @ %entry
77
; CHECK-NEXT: .save {r4, r5, r7, lr}

‎llvm/test/CodeGen/Thumb2/mve-float16regloops.ll‎

Lines changed: 38 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1004,22 +1004,22 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
10041004
; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph
10051005
; CHECK-NEXT: ldrh r4, [r0]
10061006
; CHECK-NEXT: movs r1, #1
1007-
; CHECK-NEXT: ldrd r5, r3, [r0, #4]
1007+
; CHECK-NEXT: ldrd r5, r7, [r0, #4]
10081008
; CHECK-NEXT: sub.w r0, r4, #8
1009-
; CHECK-NEXT: add.w r7, r0, r0, lsr #29
1009+
; CHECK-NEXT: add.w r3, r0, r0, lsr #29
10101010
; CHECK-NEXT: and r0, r0, #7
1011-
; CHECK-NEXT: asrs r6, r7, #3
1011+
; CHECK-NEXT: asrs r6, r3, #3
10121012
; CHECK-NEXT: cmp r6, #1
10131013
; CHECK-NEXT: it gt
1014-
; CHECK-NEXT: asrgt r1, r7, #3
1015-
; CHECK-NEXT: add.w r7, r5, r4, lsl #1
1014+
; CHECK-NEXT: asrgt r1, r3, #3
1015+
; CHECK-NEXT: add.w r3, r5, r4, lsl #1
10161016
; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
1017-
; CHECK-NEXT: subs r1, r7, #2
1018-
; CHECK-NEXT: rsbs r7, r4, #0
1019-
; CHECK-NEXT: str r7, [sp, #8] @ 4-byte Spill
1020-
; CHECK-NEXT: add.w r7, r3, #16
1017+
; CHECK-NEXT: subs r1, r3, #2
1018+
; CHECK-NEXT: rsbs r3, r4, #0
1019+
; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
1020+
; CHECK-NEXT: add.w r3, r7, #16
10211021
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
1022-
; CHECK-NEXT: str r7, [sp, #4] @ 4-byte Spill
1022+
; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
10231023
; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
10241024
; CHECK-NEXT: b .LBB16_6
10251025
; CHECK-NEXT: .LBB16_3: @ %while.end.loopexit
@@ -1045,36 +1045,36 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
10451045
; CHECK-NEXT: @ Child Loop BB16_8 Depth 2
10461046
; CHECK-NEXT: @ Child Loop BB16_11 Depth 2
10471047
; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
1048-
; CHECK-NEXT: ldrh.w lr, [r3, #14]
1048+
; CHECK-NEXT: ldrh.w lr, [r7, #14]
10491049
; CHECK-NEXT: vldrw.u32 q0, [r0], #8
1050-
; CHECK-NEXT: ldrh.w r8, [r3, #12]
1051-
; CHECK-NEXT: ldrh r7, [r3, #10]
1052-
; CHECK-NEXT: ldrh r4, [r3, #8]
1053-
; CHECK-NEXT: ldrh r6, [r3, #6]
1054-
; CHECK-NEXT: ldrh.w r9, [r3, #4]
1055-
; CHECK-NEXT: ldrh.w r11, [r3, #2]
1056-
; CHECK-NEXT: ldrh.w r10, [r3]
1050+
; CHECK-NEXT: ldrh.w r9, [r7, #12]
1051+
; CHECK-NEXT: ldrh.w r10, [r7, #10]
1052+
; CHECK-NEXT: ldrh r4, [r7, #8]
1053+
; CHECK-NEXT: ldrh r3, [r7, #6]
1054+
; CHECK-NEXT: ldrh r6, [r7, #4]
1055+
; CHECK-NEXT: ldrh.w r11, [r7, #2]
1056+
; CHECK-NEXT: ldrh.w r8, [r7]
10571057
; CHECK-NEXT: vstrb.8 q0, [r1], #8
10581058
; CHECK-NEXT: vldrw.u32 q0, [r5]
10591059
; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
10601060
; CHECK-NEXT: adds r0, r5, #2
10611061
; CHECK-NEXT: vldrw.u32 q1, [r0]
1062-
; CHECK-NEXT: vmul.f16 q0, q0, r10
1062+
; CHECK-NEXT: vmul.f16 q0, q0, r8
10631063
; CHECK-NEXT: adds r0, r5, #6
10641064
; CHECK-NEXT: vfma.f16 q0, q1, r11
10651065
; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
1066-
; CHECK-NEXT: vfma.f16 q0, q1, r9
1066+
; CHECK-NEXT: vfma.f16 q0, q1, r6
10671067
; CHECK-NEXT: vldrw.u32 q1, [r0]
10681068
; CHECK-NEXT: add.w r0, r5, #10
1069-
; CHECK-NEXT: vfma.f16 q0, q1, r6
1069+
; CHECK-NEXT: vfma.f16 q0, q1, r3
10701070
; CHECK-NEXT: vldrw.u32 q1, [r5, #8]
10711071
; CHECK-NEXT: vfma.f16 q0, q1, r4
10721072
; CHECK-NEXT: vldrw.u32 q1, [r0]
10731073
; CHECK-NEXT: add.w r0, r5, #14
1074-
; CHECK-NEXT: vfma.f16 q0, q1, r7
1074+
; CHECK-NEXT: vfma.f16 q0, q1, r10
10751075
; CHECK-NEXT: vldrw.u32 q1, [r5, #12]
10761076
; CHECK-NEXT: adds r5, #16
1077-
; CHECK-NEXT: vfma.f16 q0, q1, r8
1077+
; CHECK-NEXT: vfma.f16 q0, q1, r9
10781078
; CHECK-NEXT: vldrw.u32 q1, [r0]
10791079
; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
10801080
; CHECK-NEXT: vfma.f16 q0, q1, lr
@@ -1083,40 +1083,44 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
10831083
; CHECK-NEXT: @ %bb.7: @ %for.body.preheader
10841084
; CHECK-NEXT: @ in Loop: Header=BB16_6 Depth=1
10851085
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
1086+
; CHECK-NEXT: mov r3, r7
10861087
; CHECK-NEXT: dls lr, r0
10871088
; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
10881089
; CHECK-NEXT: .LBB16_8: @ %for.body
10891090
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
10901091
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
1091-
; CHECK-NEXT: ldrh r0, [r6], #16
1092+
; CHECK-NEXT: ldrh r0, [r3, #16]
10921093
; CHECK-NEXT: vldrw.u32 q1, [r5]
10931094
; CHECK-NEXT: adds r4, r5, #2
1095+
; CHECK-NEXT: mov r9, r6
10941096
; CHECK-NEXT: vfma.f16 q0, q1, r0
10951097
; CHECK-NEXT: vldrw.u32 q1, [r4]
1096-
; CHECK-NEXT: ldrh r0, [r6, #-14]
1098+
; CHECK-NEXT: ldrh r0, [r3, #18]
10971099
; CHECK-NEXT: adds r4, r5, #6
1100+
; CHECK-NEXT: adds r6, #16
10981101
; CHECK-NEXT: vfma.f16 q0, q1, r0
1099-
; CHECK-NEXT: ldrh r0, [r6, #-12]
1102+
; CHECK-NEXT: ldrh r0, [r3, #20]
11001103
; CHECK-NEXT: vldrw.u32 q1, [r5, #4]
11011104
; CHECK-NEXT: vfma.f16 q0, q1, r0
11021105
; CHECK-NEXT: vldrw.u32 q1, [r4]
1103-
; CHECK-NEXT: ldrh r0, [r6, #-10]
1106+
; CHECK-NEXT: ldrh r0, [r3, #22]
11041107
; CHECK-NEXT: add.w r4, r5, #10
11051108
; CHECK-NEXT: vfma.f16 q0, q1, r0
1106-
; CHECK-NEXT: ldrh r0, [r6, #-8]
1109+
; CHECK-NEXT: ldrh r0, [r3, #24]
11071110
; CHECK-NEXT: vldrw.u32 q1, [r5, #8]
11081111
; CHECK-NEXT: vfma.f16 q0, q1, r0
1112+
; CHECK-NEXT: ldrh r0, [r3, #26]
11091113
; CHECK-NEXT: vldrw.u32 q1, [r4]
1110-
; CHECK-NEXT: ldrh r0, [r6, #-6]
1111-
; CHECK-NEXT: ldrh r4, [r6, #-2]
11121114
; CHECK-NEXT: vfma.f16 q0, q1, r0
1113-
; CHECK-NEXT: ldrh r0, [r6, #-4]
1115+
; CHECK-NEXT: ldrh r0, [r3, #28]
11141116
; CHECK-NEXT: vldrw.u32 q1, [r5, #12]
1117+
; CHECK-NEXT: ldrh r3, [r3, #30]
11151118
; CHECK-NEXT: vfma.f16 q0, q1, r0
11161119
; CHECK-NEXT: add.w r0, r5, #14
11171120
; CHECK-NEXT: vldrw.u32 q1, [r0]
11181121
; CHECK-NEXT: adds r5, #16
1119-
; CHECK-NEXT: vfma.f16 q0, q1, r4
1122+
; CHECK-NEXT: vfma.f16 q0, q1, r3
1123+
; CHECK-NEXT: mov r3, r9
11201124
; CHECK-NEXT: le lr, .LBB16_8
11211125
; CHECK-NEXT: b .LBB16_4
11221126
; CHECK-NEXT: .LBB16_9: @ in Loop: Header=BB16_6 Depth=1
@@ -1128,9 +1132,9 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
11281132
; CHECK-NEXT: .LBB16_11: @ %while.body76
11291133
; CHECK-NEXT: @ Parent Loop BB16_6 Depth=1
11301134
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
1131-
; CHECK-NEXT: ldrh r4, [r6], #2
1135+
; CHECK-NEXT: ldrh r3, [r6], #2
11321136
; CHECK-NEXT: vldrh.u16 q1, [r0], #2
1133-
; CHECK-NEXT: vfma.f16 q0, q1, r4
1137+
; CHECK-NEXT: vfma.f16 q0, q1, r3
11341138
; CHECK-NEXT: le lr, .LBB16_11
11351139
; CHECK-NEXT: b .LBB16_3
11361140
; CHECK-NEXT: .LBB16_12: @ %if.end

‎llvm/test/CodeGen/Thumb2/mve-float32regloops.ll‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
33

4-
define arm_aapcs_vfpcc void @test_fadd(ptr noalias nocapture readonly %A, float %B, ptr noalias nocapture %C, i32 %n) {
4+
define arm_aapcs_vfpcc void @test_fadd(ptr noalias nocapture readonly noundef %A, float %B, ptr noalias nocapture %C, i32 %n) {
55
; CHECK-LABEL: test_fadd:
66
; CHECK: @ %bb.0: @ %entry
77
; CHECK-NEXT: cmp r2, #1
@@ -1119,9 +1119,9 @@ define void @fir(ptr nocapture readonly %S, ptr nocapture readonly %pSrc, ptr no
11191119
; CHECK-NEXT: bx lr
11201120
entry:
11211121
%pState1 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 1
1122-
%i = load ptr, ptr %pState1, align 4
1122+
%i = load ptr, ptr %pState1, align 4, !noundef !0
11231123
%pCoeffs2 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 2
1124-
%i1 = load ptr, ptr %pCoeffs2, align 4
1124+
%i1 = load ptr, ptr %pCoeffs2, align 4, !noundef !0
11251125
%numTaps3 = getelementptr inbounds %struct.arm_fir_instance_f32, ptr %S, i32 0, i32 0
11261126
%i2 = load i16, ptr %numTaps3, align 4
11271127
%conv = zext i16 %i2 to i32
@@ -2117,3 +2117,5 @@ declare void @llvm.assume(i1)
21172117
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
21182118
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
21192119
declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>)
2120+
2121+
!0 = !{}

‎llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -371,7 +371,7 @@ return:
371371
; Two phis should remain, one starting at %init, and one at %init1.
372372
; Two increments should remain, one by %step and one by %step1.
373373
; Five live-outs should remain.
374-
define i32 @isomorphic(i32 %init, i32 %step, i32 %lim) nounwind {
374+
define i32 @isomorphic(i32 noundef %init, i32 noundef %step, i32 %lim) nounwind {
375375
; CHECK-LABEL: @isomorphic(
376376
; CHECK-NEXT: entry:
377377
; CHECK-NEXT: [[STEP1:%.*]] = add i32 [[STEP:%.*]], 1

‎llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@ target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
55
target triple = "riscv64-unknown-linux-gnu"
66

77
; Test case for https://github.com/llvm/llvm-project/issues/106417.
8-
define void @skip_free_iv_truncate(i16 %x, ptr %A) #0 {
8+
define void @skip_free_iv_truncate(i16 noundef %x, ptr %A) #0 {
99
; CHECK-LABEL: define void @skip_free_iv_truncate(
10-
; CHECK-SAME: i16 [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
10+
; CHECK-SAME: i16 noundef [[X:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
1111
; CHECK-NEXT: [[ENTRY:.*]]:
1212
; CHECK-NEXT: [[X_I32:%.*]] = sext i16 [[X]] to i32
1313
; CHECK-NEXT: [[X_I64:%.*]] = sext i16 [[X]] to i64

‎llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -706,9 +706,9 @@ exit:
706706
ret void
707707
}
708708

709-
define void @wombat(i32 %arg, ptr %dst) #1 {
709+
define void @wombat(i32 noundef %arg, ptr %dst) #1 {
710710
; CHECK-LABEL: define void @wombat(
711-
; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1:[0-9]+]] {
711+
; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1:[0-9]+]] {
712712
; CHECK-NEXT: entry:
713713
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
714714
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
@@ -780,9 +780,9 @@ exit:
780780
ret void
781781
}
782782

783-
define void @wombat2(i32 %arg, ptr %dst) #1 {
783+
define void @wombat2(i32 noundef %arg, ptr %dst) #1 {
784784
; CHECK-LABEL: define void @wombat2(
785-
; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
785+
; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
786786
; CHECK-NEXT: entry:
787787
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
788788
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64
@@ -857,9 +857,9 @@ exit:
857857
}
858858

859859

860-
define void @with_dead_use(i32 %arg, ptr %dst) #1 {
860+
define void @with_dead_use(i32 noundef %arg, ptr %dst) #1 {
861861
; CHECK-LABEL: define void @with_dead_use(
862-
; CHECK-SAME: i32 [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
862+
; CHECK-SAME: i32 noundef [[ARG:%.*]], ptr [[DST:%.*]]) #[[ATTR1]] {
863863
; CHECK-NEXT: entry:
864864
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ARG]], 3
865865
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG]] to i64

‎llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -128,9 +128,9 @@ exit:
128128
ret i32 0
129129
}
130130

131-
define void @test_scalar_cost_single_store_loop_invariant_cond(ptr %dst, i1 %c) #0 {
131+
define void @test_scalar_cost_single_store_loop_invariant_cond(ptr noundef %dst, i1 %c) #0 {
132132
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_invariant_cond(
133-
; CHECK-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {
133+
; CHECK-SAME: ptr noundef [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR0]] {
134134
; CHECK-NEXT: entry:
135135
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
136136
; CHECK: vector.ph:
@@ -191,9 +191,9 @@ exit:
191191
ret void
192192
}
193193

194-
define void @test_scalar_cost_single_store_loop_varying_cond(ptr %dst, ptr noalias %src) #0 {
194+
define void @test_scalar_cost_single_store_loop_varying_cond(ptr noundef %dst, ptr noalias %src) #0 {
195195
; CHECK-LABEL: define void @test_scalar_cost_single_store_loop_varying_cond(
196-
; CHECK-SAME: ptr [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
196+
; CHECK-SAME: ptr noundef [[DST:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
197197
; CHECK-NEXT: entry:
198198
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
199199
; CHECK: vector.ph:

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