Move constant XOR AND ANDNOT optimization to generic DAG combiner

This moves the optimization from X86-specific code to the generic
reassociateOpsCommutative function in DAGCombiner.cpp. The optimization
transforms (Constant XOR a) & b & ~c -> (Constant XOR a) & (b & ~c)
to allow ANDNOT operations to be done in parallel with XOR operations.

This benefits all targets that have ANDNOT instructions (X86 BMI, ARM BIC,
RISC-V, etc.) rather than being limited to X86 only.

- Remove X86-specific combineConstantXorAndAndNot function
- Add generic optimization to reassociateOpsCommutative with TLI.hasAndNot check
- Update test expectations for the new optimized output

Author: manik-muk

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -1262,6 +1262,41 @@ SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
     if (N1 == N00 || N1 == N01)
       return N0;
   }
+
+  // Optimize (Constant XOR a) & b & ~c -> (Constant XOR a) & (b & ~c)
+  // This allows the andn operation to be done in parallel with the xor
+  if (Opc == ISD::AND && TLI.hasAndNot(N1)) {
+    // Look for pattern: AND(AND(XOR(Constant, a), b), NOT(c))
+    // Transform to: AND(XOR(Constant, a), AND(b, NOT(c)))
+    
+    // Check if N1 is NOT(c) - i.e., XOR(c, -1)
+    if (N1.getOpcode() == ISD::XOR && 
+        DAG.isConstantIntBuildVectorOrConstantInt(N1.getOperand(1)) &&
+        isAllOnesConstant(N1.getOperand(1))) {
+      
+      // Check if one operand of N0 is XOR(Constant, a)
+      SDValue XorOp, OtherOp;
+      if (N00.getOpcode() == ISD::XOR) {
+        XorOp = N00;
+        OtherOp = N01;
+      } else if (N01.getOpcode() == ISD::XOR) {
+        XorOp = N01;
+        OtherOp = N00;
+      } else {
+        return SDValue();
+      }
+      
+      // Check if XOR has a constant operand
+      if (DAG.isConstantIntBuildVectorOrConstantInt(XorOp.getOperand(0)) ||
+          DAG.isConstantIntBuildVectorOrConstantInt(XorOp.getOperand(1))) {
+        // Transform: AND(AND(XOR(Constant, a), b), NOT(c))
+        // To: AND(XOR(Constant, a), AND(b, NOT(c)))
+        // This allows the andn (b & ~c) to be done in parallel with the xor
+        SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, OtherOp, N1);
+        return DAG.getNode(ISD::AND, DL, VT, XorOp, NewAnd);
+      }
+    }
+  }
   if (Opc == ISD::XOR) {
     // (N00 ^ N01) ^ N00 --> N01
     if (N1 == N00)

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -51541,63 +51541,6 @@ static SDValue combineBMILogicOp(SDNode *N, SelectionDAG &DAG,
   return SDValue();
 }
 
-/// Optimize (Constant XOR a) & b & ~c -> (Constant XOR a) & (b & ~c)
-/// This allows the andn operation to be done in parallel with the xor
-static SDValue combineConstantXorAndAndNot(SDNode *N, const SDLoc &DL,
-                                           SelectionDAG &DAG,
-                                           const X86Subtarget &Subtarget) {
-  using namespace llvm::SDPatternMatch;
-
-  EVT VT = N->getValueType(0);
-  // Only handle scalar integer types that support BMI instructions
-  if (!Subtarget.hasBMI() || (VT != MVT::i32 && VT != MVT::i64))
-    return SDValue();
-
-  SDValue N0 = N->getOperand(0);
-  SDValue N1 = N->getOperand(1);
-
-  // Check if N0 is AND(XOR(Constant, a), b)
-  if (N0.getOpcode() != ISD::AND)
-    return SDValue();
-
-  SDValue AndLHS = N0.getOperand(0);
-  SDValue AndRHS = N0.getOperand(1);
-
-  // Check if one operand is XOR(Constant, a)
-  SDValue XorOp, OtherOp;
-  if (AndLHS.getOpcode() == ISD::XOR) {
-    XorOp = AndLHS;
-    OtherOp = AndRHS;
-  } else if (AndRHS.getOpcode() == ISD::XOR) {
-    XorOp = AndRHS;
-    OtherOp = AndLHS;
-  } else {
-    return SDValue();
-  }
-
-  // Check if XOR has a constant operand
-  if (!isa<ConstantSDNode>(XorOp.getOperand(0)) &&
-      !isa<ConstantSDNode>(XorOp.getOperand(1))) {
-    return SDValue();
-  }
-
-  // Check if N1 is NOT(c) - i.e., XOR(c, -1)
-  SDValue NotOp;
-  if (N1.getOpcode() == ISD::XOR && isAllOnesConstant(N1.getOperand(1))) {
-    NotOp = N1.getOperand(0);
-  } else {
-    return SDValue();
-  }
-
-  // Transform: AND(AND(XOR(Constant, a), b), NOT(c))
-  // To: AND(XOR(Constant, a), AND(b, NOT(c)))
-  // This allows the andn (b & ~c) to be done in parallel with the xor
-
-  // Create AND(b, NOT(c)) - this will become andn
-  SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, OtherOp, N1);
-  // Create final AND(XOR(Constant, a), AND(b, NOT(c)))
-  return DAG.getNode(ISD::AND, DL, VT, XorOp, NewAnd);
-}
 
 /// Fold AND(Y, XOR(X, NEG(X))) -> ANDN(Y, BLSMSK(X)) if BMI is available.
 static SDValue combineAndXorSubWithBMI(SDNode *And, const SDLoc &DL,
@@ -51891,11 +51834,6 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
   if (SDValue R = combineAndNotOrIntoAndNotAnd(N, dl, DAG))
     return R;
 
-  // Optimize (Constant XOR a) & b & ~c -> (Constant XOR a) & (b & ~c)
-  // This allows the andn operation to be done in parallel with the xor
-  if (SDValue R = combineConstantXorAndAndNot(N, dl, DAG, Subtarget))
-    return R;
-
   // fold (and (mul x, c1), c2) -> (mul x, (and c1, c2))
   // iff c2 is all/no bits mask - i.e. a select-with-zero mask.
   // TODO: Handle PMULDQ/PMULUDQ/VPMADDWD/VPMADDUBSW?

llvm/test/CodeGen/X86/constant-xor-and-andnot.ll

@@ -52,8 +52,8 @@ define i64 @test_constant_xor_and_andnot_final_swapped(i64 %a, i64 %b, i64 %c) {
 ; CHECK-LABEL: test_constant_xor_and_andnot_final_swapped:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorq $1234, %rdi # imm = 0x4D2
-; CHECK-NEXT:    andq %rsi, %rdi
-; CHECK-NEXT:    andnq %rdi, %rdx, %rax
+; CHECK-NEXT:    andnq %rsi, %rdx, %rax
+; CHECK-NEXT:    andq %rdi, %rax
 ; CHECK-NEXT:    retq
   %xor = xor i64 %a, 1234
   %and1 = and i64 %xor, %b