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[uArch][XeGPU] Add XeGPU uArch definition.
The uArch infrastructure provides: - A set data structures to represent, uArch and it's necessary components (e.g., instructions, register-files, caches). - A set of utility interfaces that are common to a family of ops (e.g., mma ops, 2DBlockIO ops). The implementation of these interfaces are provided by the specific instructions. Each family of ops provides these 5 common APIs. However, some family of ops may have more utility APIs. The common 5 APIs are: - getSupportedShapes - getSupportedTypes - checkSupportedShapesAndTypes - checkSupportedTypes - validate Add support for PVC and BMG architectures. Add support for DPAS instruction.
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‎mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h‎

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//===--- IntelGpuXe2.h ---------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Xe2 uArch definition.
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///
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_DIALECT_XEGPU_UARCH_INTEL_GPU_XE2_H
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#define MLIR_DIALECT_XEGPU_UARCH_INTEL_GPU_XE2_H
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#include "mlir/Dialect/XeGPU/uArch/uArchInterfaces.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/TypeUtilities.h"
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#include <map>
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#include <string>
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#include <vector>
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namespace mlir {
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namespace xegpu {
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namespace uArch {
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namespace Xe2Plus {
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struct XeCoreInfo {
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uint32_t num_threads;
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SharedMemory shared_memory;
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uint32_t num_vector_units;
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uint32_t num_matrix_units;
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// Constructor
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XeCoreInfo(uint32_t num_threads, const SharedMemory &shared_memory,
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uint32_t num_vector_units, uint32_t num_matrix_units)
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: num_threads(num_threads), shared_memory(shared_memory),
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num_vector_units(num_vector_units), num_matrix_units(num_matrix_units) {
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}
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};
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struct Xe2Plus : public uArch {
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XeCoreInfo xe_core;
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Xe2Plus(
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const std::string &archName, const std::string &archDescription,
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const XeCoreInfo &xeCore,
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const std::vector<uArchHierarchyComponent> &hierarchy = {},
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const std::map<std::string, RegisterFileInfo> &regInfo = {},
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const std::vector<CacheInfo> &cacheInfo = {},
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const std::map<std::string, std::shared_ptr<Instruction>> &instrs = {})
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: uArch(archName, archDescription, hierarchy, regInfo, cacheInfo, instrs),
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xe_core(xeCore) {}
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};
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// struct to represent DPAS instruction
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struct DPASInstruction : public Instruction, public MMAInstructionInterface {
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DPASInstruction()
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: Instruction("dpas", // name
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"Dot Product Accumulate") // description
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{}
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// Override all virtuals from MatrixOpInterface
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virtual std::vector<std::pair<uint32_t, uint32_t>>
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getSupportedShapes(mlir::Type dataType, MMAOpndEnum matrixType) override;
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virtual std::vector<mlir::Type>
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getSupportedTypes(MLIRContext &context, MMAOpndEnum matrixType) override;
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virtual bool
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checkSupportedShapesAndTypes(std::pair<uint32_t, uint32_t> AShape,
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std::pair<uint32_t, uint32_t> BShape,
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std::pair<uint32_t, uint32_t> CShape,
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std::pair<uint32_t, uint32_t> DShape,
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mlir::Type AType, mlir::Type BType,
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mlir::Type CType, mlir::Type DType) override;
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virtual bool checkSupportedTypes(mlir::Type AType, mlir::Type BType,
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mlir::Type CType, mlir::Type DType) override;
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virtual bool validate(std::pair<uint32_t, uint32_t> AShape,
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std::pair<uint32_t, uint32_t> BShape,
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std::pair<uint32_t, uint32_t> CShape,
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std::pair<uint32_t, uint32_t> DShape, mlir::Type AType,
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mlir::Type BType, mlir::Type CType,
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mlir::Type DType) override;
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virtual std::vector<uint32_t> getSupportedM(mlir::Type type) override;
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virtual std::vector<uint32_t> getSupportedK(mlir::Type type) override;
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virtual std::vector<uint32_t> getSupportedN(mlir::Type type) override;
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};
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namespace PVCuArch {
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struct PVCuArch : public Xe2Plus {
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// Maintaines ownership of the instructions owned by PVUarch
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std::vector<std::shared_ptr<Instruction>> owned_instructions;
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PVCuArch()
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: Xe2Plus("pvc", // archName
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"Ponte Vecchio Architecture", // archDescription
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XeCoreInfo(8, SharedMemory(512 * 1024, 4), 8, 8), // xeCore
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{/* register_file_info */}, // Optional: empty
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{/* cache_info */}, // Optional: empty
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{/* instructions */} // Optional: empty
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) {
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// Initialize uArchHierarchy
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("thread", 0));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("XeCore", 8));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("XeSlice", 16));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("XeStack", 4));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("gpu", 2));
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// Intialize register file info
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// GRF
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this->register_file_info.emplace(
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"GRF",
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RegisterFileInfo(64 * 1024, // size in bits
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{"small", "large"}, // GRF modes
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{128, 256}, // registers per thread per mode
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0, // number of banks
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0 // bank size
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));
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// Initialize cache info
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// L1 cache, XeCore level
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this->cache_info.push_back(
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CacheInfo(512 * 1024, 64, this->uArch_hierarchy[1]));
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// L3 cache, XeStack level
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this->cache_info.push_back(
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CacheInfo(512 * 1024, 64, this->uArch_hierarchy[3]));
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// Add the instructions
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auto dpas = std::make_shared<DPASInstruction>();
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instructions.emplace(dpas->getName(), dpas);
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// instructions[dpas->name] = dpas.get();
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owned_instructions.push_back(dpas);
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}
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};
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} // namespace PVCuArch
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namespace BMGuArch {
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struct BMGuArch : public Xe2Plus {
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// Maintaines ownership of the instructions owned by PVUarch
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std::vector<std::shared_ptr<Instruction>> owned_instructions;
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BMGuArch()
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: Xe2Plus("bmg", // archName
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"Battlemage Architecture", // archDescription
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XeCoreInfo(8, SharedMemory(256 * 1024, 4), 8, 8), // xeCore
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{/* register_file_info */}, // Optional: empty
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{/* cache_info */}, // Optional: empty
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{/* instructions */}, // Optional: empty
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{/* restrictions */} // Optional: empty
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) {
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// Initialize uArchHierarchy
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("thread", 0));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("XeCore", 8));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("XeSlice", 4));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("XeStack", 5));
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this->uArch_hierarchy.push_back(uArchHierarchyComponent("gpu", 1));
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// Intialize register file info
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// GRF
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this->register_file_info["GRF"] =
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RegisterFileInfo(64 * 1024, // size in bits
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{"small", "large"}, // GRF modes
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{128, 256}, // registers per thread per mode
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0, // number of banks
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0 // bank size
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);
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// Initialize cache info
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// L1 cache, XeCore level
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this->cache_info.push_back(
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CacheInfo(256 * 1024, 64, this->uArch_hierarchy[1]));
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// L3 cache, XeStack level
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this->cache_info.push_back(
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CacheInfo(18 * 1024 * 1024, 256, this->uArch_hierarchy[3]));
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// Add the instructions
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auto dpas = std::make_shared<DPASInstruction>();
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instructions.emplace(dpas->getName(), dpas);
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// instructions[dpas->name] = dpas.get();
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owned_instructions.push_back(dpas);
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}
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};
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} // namespace BMGuArch
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} // namespace Xe2Plus
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} // namespace uArch
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} // namespace xegpu
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} // namespace mlir
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#endif // MLIR_DIALECT_XEGPU_UARCH_INTEL_GPU_XE2_H

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