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ShoreshenShoreshen
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fix comments
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2 files changed

+58
-138
lines changed

2 files changed

+58
-138
lines changed

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 28 additions & 118 deletions
Original file line numberDiff line numberDiff line change
@@ -1595,15 +1595,8 @@ foreach Index = 0-31 in {
15951595
foreach vt = Reg16Types.types in {
15961596
foreach st = Reg16Types.types in {
15971597
if !not(!eq (vt, st)) then {
1598-
def : BitConvert <vt, st, VGPR_32>;
1599-
}
1600-
}
1601-
}
1602-
1603-
foreach vt = Reg16Types.types in {
1604-
foreach st = Reg16Types.types in {
1605-
if !not(!eq (vt, st)) then {
1606-
def : BitConvert <vt, st, SReg_32>;
1598+
def : BitConvert <vt, st, VGPR_32>;
1599+
def : BitConvert <vt, st, SReg_32>;
16071600
}
16081601
}
16091602
}
@@ -1612,15 +1605,8 @@ foreach vt = Reg16Types.types in {
16121605
foreach vt = Reg32DataTypes.types in {
16131606
foreach st = Reg32DataTypes.types in {
16141607
if !not(!eq (vt, st)) then {
1615-
def : BitConvert <vt, st, VGPR_32>;
1616-
}
1617-
}
1618-
}
1619-
1620-
foreach vt = Reg32DataTypes.types in {
1621-
foreach st = Reg32DataTypes.types in {
1622-
if !not(!eq (vt, st)) then {
1623-
def : BitConvert <vt, st, SReg_32>;
1608+
def : BitConvert <vt, st, VGPR_32>;
1609+
def : BitConvert <vt, st, SReg_32>;
16241610
}
16251611
}
16261612
}
@@ -1630,7 +1616,7 @@ foreach vt = Reg32DataTypes.types in {
16301616
foreach vt = Reg64DataTypes.types in {
16311617
foreach st = Reg64DataTypes.types in {
16321618
if !not(!eq (vt, st)) then {
1633-
def : BitConvert <vt, st, VReg_64>;
1619+
def : BitConvert <vt, st, VReg_64>;
16341620
}
16351621
}
16361622
}
@@ -1640,7 +1626,7 @@ foreach vt = Reg64DataTypes.types in {
16401626
foreach vt = SGPR_96.RegTypes in {
16411627
foreach st = SGPR_96.RegTypes in {
16421628
if !not(!eq (vt, st)) then {
1643-
def : BitConvert <vt, st, SGPR_96>;
1629+
def : BitConvert <vt, st, SGPR_96>;
16441630
}
16451631
}
16461632
}
@@ -1650,15 +1636,8 @@ foreach vt = SGPR_96.RegTypes in {
16501636
foreach vt = VReg_128.RegTypes in {
16511637
foreach st = VReg_128.RegTypes in {
16521638
if !not(!eq (vt, st)) then {
1653-
def : BitConvert <vt, st, VReg_128>;
1654-
}
1655-
}
1656-
}
1657-
1658-
foreach vt = SReg_128.RegTypes in {
1659-
foreach st = SReg_128.RegTypes in {
1660-
if !not(!eq (vt, st)) then {
1661-
def : BitConvert <vt, st, SReg_128>;
1639+
def : BitConvert <vt, st, VReg_128>;
1640+
def : BitConvert <vt, st, SReg_128>;
16621641
}
16631642
}
16641643
}
@@ -1668,15 +1647,8 @@ foreach vt = SReg_128.RegTypes in {
16681647
foreach vt = VReg_160.RegTypes in {
16691648
foreach st = VReg_160.RegTypes in {
16701649
if !not(!eq (vt, st)) then {
1671-
def : BitConvert <vt, st, VReg_160>;
1672-
}
1673-
}
1674-
}
1675-
1676-
foreach vt = SReg_160.RegTypes in {
1677-
foreach st = SReg_160.RegTypes in {
1678-
if !not(!eq (vt, st)) then {
1679-
def : BitConvert <vt, st, SReg_160>;
1650+
def : BitConvert <vt, st, VReg_160>;
1651+
def : BitConvert <vt, st, SReg_160>;
16801652
}
16811653
}
16821654
}
@@ -1685,15 +1657,8 @@ foreach vt = SReg_160.RegTypes in {
16851657
foreach vt = VReg_192.RegTypes in {
16861658
foreach st = VReg_192.RegTypes in {
16871659
if !not(!eq (vt, st)) then {
1688-
def : BitConvert <vt, st, VReg_192>;
1689-
}
1690-
}
1691-
}
1692-
1693-
foreach vt = SReg_192.RegTypes in {
1694-
foreach st = SReg_192.RegTypes in {
1695-
if !not(!eq (vt, st)) then {
1696-
def : BitConvert <vt, st, SReg_192>;
1660+
def : BitConvert <vt, st, VReg_192>;
1661+
def : BitConvert <vt, st, SReg_192>;
16971662
}
16981663
}
16991664
}
@@ -1702,15 +1667,8 @@ foreach vt = SReg_192.RegTypes in {
17021667
foreach vt = VReg_224.RegTypes in {
17031668
foreach st = VReg_224.RegTypes in {
17041669
if !not(!eq (vt, st)) then {
1705-
def : BitConvert <vt, st, VReg_224>;
1706-
}
1707-
}
1708-
}
1709-
1710-
foreach vt = SReg_224.RegTypes in {
1711-
foreach st = SReg_224.RegTypes in {
1712-
if !not(!eq (vt, st)) then {
1713-
def : BitConvert <vt, st, SReg_224>;
1670+
def : BitConvert <vt, st, VReg_224>;
1671+
def : BitConvert <vt, st, SReg_224>;
17141672
}
17151673
}
17161674
}
@@ -1720,15 +1678,8 @@ foreach vt = SReg_224.RegTypes in {
17201678
foreach vt = VReg_256.RegTypes in {
17211679
foreach st = VReg_256.RegTypes in {
17221680
if !not(!eq (vt, st)) then {
1723-
def : BitConvert <vt, st, VReg_256>;
1724-
}
1725-
}
1726-
}
1727-
1728-
foreach vt = SReg_256.RegTypes in {
1729-
foreach st = SReg_256.RegTypes in {
1730-
if !not(!eq (vt, st)) then {
1731-
def : BitConvert <vt, st, SReg_256>;
1681+
def : BitConvert <vt, st, VReg_256>;
1682+
def : BitConvert <vt, st, SReg_256>;
17321683
}
17331684
}
17341685
}
@@ -1738,15 +1689,8 @@ foreach vt = SReg_256.RegTypes in {
17381689
foreach vt = VReg_288.RegTypes in {
17391690
foreach st = VReg_288.RegTypes in {
17401691
if !not(!eq (vt, st)) then {
1741-
def : BitConvert <vt, st, VReg_288>;
1742-
}
1743-
}
1744-
}
1745-
1746-
foreach vt = SReg_288.RegTypes in {
1747-
foreach st = SReg_288.RegTypes in {
1748-
if !not(!eq (vt, st)) then {
1749-
def : BitConvert <vt, st, SReg_288>;
1692+
def : BitConvert <vt, st, VReg_288>;
1693+
def : BitConvert <vt, st, SReg_288>;
17501694
}
17511695
}
17521696
}
@@ -1755,15 +1699,8 @@ foreach vt = SReg_288.RegTypes in {
17551699
foreach vt = VReg_320.RegTypes in {
17561700
foreach st = VReg_320.RegTypes in {
17571701
if !not(!eq (vt, st)) then {
1758-
def : BitConvert <vt, st, VReg_320>;
1759-
}
1760-
}
1761-
}
1762-
1763-
foreach vt = SReg_320.RegTypes in {
1764-
foreach st = SReg_320.RegTypes in {
1765-
if !not(!eq (vt, st)) then {
1766-
def : BitConvert <vt, st, SReg_320>;
1702+
def : BitConvert <vt, st, VReg_320>;
1703+
def : BitConvert <vt, st, SReg_320>;
17671704
}
17681705
}
17691706
}
@@ -1772,15 +1709,8 @@ foreach vt = SReg_320.RegTypes in {
17721709
foreach vt = VReg_352.RegTypes in {
17731710
foreach st = VReg_352.RegTypes in {
17741711
if !not(!eq (vt, st)) then {
1775-
def : BitConvert <vt, st, VReg_352>;
1776-
}
1777-
}
1778-
}
1779-
1780-
foreach vt = SReg_352.RegTypes in {
1781-
foreach st = SReg_352.RegTypes in {
1782-
if !not(!eq (vt, st)) then {
1783-
def : BitConvert <vt, st, SReg_352>;
1712+
def : BitConvert <vt, st, VReg_352>;
1713+
def : BitConvert <vt, st, SReg_352>;
17841714
}
17851715
}
17861716
}
@@ -1789,15 +1719,8 @@ foreach vt = SReg_352.RegTypes in {
17891719
foreach vt = VReg_384.RegTypes in {
17901720
foreach st = VReg_384.RegTypes in {
17911721
if !not(!eq (vt, st)) then {
1792-
def : BitConvert <vt, st, VReg_384>;
1793-
}
1794-
}
1795-
}
1796-
1797-
foreach vt = SReg_384.RegTypes in {
1798-
foreach st = SReg_384.RegTypes in {
1799-
if !not(!eq (vt, st)) then {
1800-
def : BitConvert <vt, st, SReg_384>;
1722+
def : BitConvert <vt, st, VReg_384>;
1723+
def : BitConvert <vt, st, SReg_384>;
18011724
}
18021725
}
18031726
}
@@ -1806,32 +1729,19 @@ foreach vt = SReg_384.RegTypes in {
18061729
foreach vt = VReg_512.RegTypes in {
18071730
foreach st = VReg_512.RegTypes in {
18081731
if !not(!eq (vt, st)) then {
1809-
def : BitConvert <vt, st, VReg_512>;
1732+
def : BitConvert <vt, st, VReg_512>;
1733+
def : BitConvert <vt, st, SReg_512>;
18101734
}
18111735
}
18121736
}
18131737

1814-
foreach vt = SReg_512.RegTypes in {
1815-
foreach st = SReg_512.RegTypes in {
1816-
if !not(!eq (vt, st)) then {
1817-
def : BitConvert <vt, st, SReg_512>;
1818-
}
1819-
}
1820-
}
18211738

18221739
// 1024-bit bitcast
18231740
foreach vt = VReg_1024.RegTypes in {
18241741
foreach st = VReg_1024.RegTypes in {
18251742
if !not(!eq (vt, st)) then {
1826-
def : BitConvert <vt, st, VReg_1024>;
1827-
}
1828-
}
1829-
}
1830-
1831-
foreach vt = SReg_1024.RegTypes in {
1832-
foreach st = SReg_1024.RegTypes in {
1833-
if !not(!eq (vt, st)) then {
1834-
def : BitConvert <vt, st, SReg_1024>;
1743+
def : BitConvert <vt, st, VReg_1024>;
1744+
def : BitConvert <vt, st, SReg_1024>;
18351745
}
18361746
}
18371747
}

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 30 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -555,6 +555,16 @@ def Reg64PtrTypes: RegisterTypes<[p0, p1, p4]>;
555555
def Reg64Types : RegisterTypes<!listconcat(Reg64DataTypes.types, Reg64PtrTypes.types)>;
556556
def Reg96Types : RegisterTypes<[v3i32, v3f32]>;
557557
def Reg128Types : RegisterTypes<[v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16]>;
558+
def Reg160Types : RegisterTypes<[v5i32, v5f32]>;
559+
def Reg192Types : RegisterTypes<[v6i32, v6f32, v3i64, v3f64]>;
560+
def Reg224Types : RegisterTypes<[v7i32, v7f32]>;
561+
def Reg256Types : RegisterTypes<[v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16]>;
562+
def Reg288Types : RegisterTypes<[v9i32, v9f32]>;
563+
def Reg320Types : RegisterTypes<[v10i32, v10f32]>;
564+
def Reg352Types : RegisterTypes<[v11i32, v11f32]>;
565+
def Reg384Types : RegisterTypes<[v12i32, v12f32]>;
566+
def Reg512Types : RegisterTypes<[v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16]>;
567+
def Reg1024Types : RegisterTypes<[v32i32, v32f32, v16i64, v16f64]>;
558568

559569
let HasVGPR = 1 in {
560570
// VOP3 and VINTERP can access 256 lo and 256 hi registers.
@@ -895,18 +905,18 @@ multiclass SRegClass<int numRegs,
895905

896906
defm "" : SRegClass<3, Reg96Types.types, SGPR_96Regs, TTMP_96Regs>;
897907
defm "" : SRegClass<4, Reg128Types.types, SGPR_128Regs, TTMP_128Regs, /*hasNull*/ true>;
898-
defm "" : SRegClass<5, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>;
899-
defm "" : SRegClass<6, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>;
900-
defm "" : SRegClass<7, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>;
901-
defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], SGPR_256Regs, TTMP_256Regs, /*hasNull*/ true>;
902-
defm "" : SRegClass<9, [v9i32, v9f32], SGPR_288Regs, TTMP_288Regs>;
903-
defm "" : SRegClass<10, [v10i32, v10f32], SGPR_320Regs, TTMP_320Regs>;
904-
defm "" : SRegClass<11, [v11i32, v11f32], SGPR_352Regs, TTMP_352Regs>;
905-
defm "" : SRegClass<12, [v12i32, v12f32], SGPR_384Regs, TTMP_384Regs>;
908+
defm "" : SRegClass<5, Reg160Types.types, SGPR_160Regs, TTMP_160Regs>;
909+
defm "" : SRegClass<6, Reg192Types.types, SGPR_192Regs, TTMP_192Regs>;
910+
defm "" : SRegClass<7, Reg224Types.types, SGPR_224Regs, TTMP_224Regs>;
911+
defm "" : SRegClass<8, Reg256Types.types, SGPR_256Regs, TTMP_256Regs, /*hasNull*/ true>;
912+
defm "" : SRegClass<9, Reg288Types.types, SGPR_288Regs, TTMP_288Regs>;
913+
defm "" : SRegClass<10, Reg320Types.types, SGPR_320Regs, TTMP_320Regs>;
914+
defm "" : SRegClass<11, Reg352Types.types, SGPR_352Regs, TTMP_352Regs>;
915+
defm "" : SRegClass<12, Reg384Types.types, SGPR_384Regs, TTMP_384Regs>;
906916

907917
let GlobalPriority = true in {
908-
defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], SGPR_512Regs, TTMP_512Regs>;
909-
defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>;
918+
defm "" : SRegClass<16, Reg512Types.types, SGPR_512Regs, TTMP_512Regs>;
919+
defm "" : SRegClass<32, Reg1024Types.types, SGPR_1024Regs>;
910920
}
911921

912922
def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
@@ -947,19 +957,19 @@ multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {
947957
defm VReg_64 : VRegClass<2, Reg64Types.types, (add VGPR_64)>;
948958
defm VReg_96 : VRegClass<3, Reg96Types.types, (add VGPR_96)>;
949959
defm VReg_128 : VRegClass<4, Reg128Types.types, (add VGPR_128)>;
950-
defm VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>;
960+
defm VReg_160 : VRegClass<5, Reg160Types.types, (add VGPR_160)>;
951961

952-
defm VReg_192 : VRegClass<6, [v6i32, v6f32, v3i64, v3f64], (add VGPR_192)>;
953-
defm VReg_224 : VRegClass<7, [v7i32, v7f32], (add VGPR_224)>;
954-
defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], (add VGPR_256)>;
955-
defm VReg_288 : VRegClass<9, [v9i32, v9f32], (add VGPR_288)>;
956-
defm VReg_320 : VRegClass<10, [v10i32, v10f32], (add VGPR_320)>;
957-
defm VReg_352 : VRegClass<11, [v11i32, v11f32], (add VGPR_352)>;
958-
defm VReg_384 : VRegClass<12, [v12i32, v12f32], (add VGPR_384)>;
962+
defm VReg_192 : VRegClass<6, Reg192Types.types, (add VGPR_192)>;
963+
defm VReg_224 : VRegClass<7, Reg224Types.types, (add VGPR_224)>;
964+
defm VReg_256 : VRegClass<8, Reg256Types.types, (add VGPR_256)>;
965+
defm VReg_288 : VRegClass<9, Reg288Types.types, (add VGPR_288)>;
966+
defm VReg_320 : VRegClass<10, Reg320Types.types, (add VGPR_320)>;
967+
defm VReg_352 : VRegClass<11, Reg352Types.types, (add VGPR_352)>;
968+
defm VReg_384 : VRegClass<12, Reg384Types.types, (add VGPR_384)>;
959969

960970
let GlobalPriority = true in {
961-
defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], (add VGPR_512)>;
962-
defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
971+
defm VReg_512 : VRegClass<16, Reg512Types.types, (add VGPR_512)>;
972+
defm VReg_1024 : VRegClass<32, Reg1024Types.types, (add VGPR_1024)>;
963973
}
964974

965975
multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> {

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