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correct ReadNone/ReadOnly function attributes
- correct all uses of ReadOnly/ReadNone to be consistent with hctdb.py in DXC - all fix order of attributes in each op
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llvm/lib/Target/DirectX/DXIL.td

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -783,6 +783,7 @@ def CreateHandle : DXILOp<57, createHandle> {
783783
let arguments = [Int8Ty, Int32Ty, Int32Ty, Int1Ty];
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let result = HandleTy;
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let stages = [Stages<DXIL1_0, [all_stages]>, Stages<DXIL1_6, [removed]>];
786+
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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}
787788

788789
def BufferLoad : DXILOp<68, bufferLoad> {
@@ -794,6 +795,7 @@ def BufferLoad : DXILOp<68, bufferLoad> {
794795
[Overloads<DXIL1_0,
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[ResRetHalfTy, ResRetFloatTy, ResRetInt16Ty, ResRetInt32Ty]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
798+
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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}
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799801
def BufferStore : DXILOp<69, bufferStore> {
@@ -822,6 +824,7 @@ def CheckAccessFullyMapped : DXILOp<71, checkAccessFullyMapped> {
822824
let result = Int1Ty;
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let overloads = [Overloads<DXIL1_0, [Int32Ty]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
827+
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
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}
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827830
def Discard : DXILOp<82, discard> {
@@ -896,8 +899,8 @@ def Dot4AddI8Packed : DXILOp<163, dot4AddPacked> {
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let intrinsics = [ IntrinSelect<int_dx_dot4add_i8packed> ];
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let arguments = [Int32Ty, Int32Ty, Int32Ty];
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let result = Int32Ty;
899-
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
900902
let stages = [Stages<DXIL1_0, [all_stages]>];
903+
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
902905

903906
def Dot4AddU8Packed : DXILOp<164, dot4AddPacked> {
@@ -906,22 +909,24 @@ def Dot4AddU8Packed : DXILOp<164, dot4AddPacked> {
906909
let intrinsics = [ IntrinSelect<int_dx_dot4add_u8packed> ];
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let arguments = [Int32Ty, Int32Ty, Int32Ty];
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let result = Int32Ty;
909-
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
913+
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
912915

913916
def AnnotateHandle : DXILOp<216, annotateHandle> {
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let Doc = "annotate handle with resource properties";
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let arguments = [HandleTy, ResPropsTy];
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let result = HandleTy;
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let stages = [Stages<DXIL1_6, [all_stages]>];
921+
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
919923

920924
def CreateHandleFromBinding : DXILOp<217, createHandleFromBinding> {
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let Doc = "create resource handle from binding";
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let arguments = [ResBindTy, Int32Ty, Int1Ty];
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let result = HandleTy;
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let stages = [Stages<DXIL1_6, [all_stages]>];
929+
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
926931

927932
def WaveActiveAnyTrue : DXILOp<113, waveAnyTrue> {
@@ -938,7 +943,6 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
938943
let arguments = [];
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let result = Int1Ty;
940945
let stages = [Stages<DXIL1_0, [all_stages]>];
941-
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
942946
}
943947

944948
def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
@@ -948,7 +952,6 @@ def WaveReadLaneAt: DXILOp<117, waveReadLaneAt> {
948952
let result = OverloadTy;
949953
let overloads = [Overloads<DXIL1_0, [HalfTy, FloatTy, DoubleTy, Int1Ty, Int16Ty, Int32Ty, Int64Ty]>];
950954
let stages = [Stages<DXIL1_0, [all_stages]>];
951-
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
952955
}
953956

954957
def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
@@ -957,7 +960,7 @@ def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
957960
let arguments = [];
958961
let result = Int32Ty;
959962
let stages = [Stages<DXIL1_0, [all_stages]>];
960-
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
963+
let attributes = [Attributes<DXIL1_0, [ReadOnly]>];
961964
}
962965

963966
def WaveAllBitCount : DXILOp<135, waveAllOp> {
@@ -966,7 +969,6 @@ def WaveAllBitCount : DXILOp<135, waveAllOp> {
966969
let arguments = [Int1Ty];
967970
let result = Int32Ty;
968971
let stages = [Stages<DXIL1_0, [all_stages]>];
969-
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
970972
}
971973

972974
def Barrier : DXILOp<80, barrier> {

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