Comment out-of-line patterns

Author: s-barannikov

llvm/lib/Target/ARM/ARMInstrInfo.td

@@ -5107,6 +5107,10 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
 
 } // hasSideEffects
 
+// The following patterns have to be defined out-of-line because the number
+// of instruction operands does not match the number of SDNode operands
+// (`pred` counts as one operand).
+
 def : ARMPat<(ARMcmov i32:$false, i32:$Rm, imm:$cc, CPSR),
              (MOVCCr $false, $Rm, imm:$cc, CPSR)>;
 

llvm/lib/Target/ARM/ARMInstrThumb2.td

@@ -3592,6 +3592,10 @@ def t2MOVCCi32imm
 
 } // hasSideEffects
 
+// The following patterns have to be defined out-of-line because the number
+// of instruction operands does not match the number of SDNode operands
+// (`pred` counts as one operand).
+
 def : T2Pat<(ARMcmov i32:$false, i32:$Rm, imm:$cc, CPSR),
             (t2MOVCCr $false, $Rm, imm:$cc, CPSR)>;
 

llvm/lib/Target/ARM/ARMInstrVFP.td

@@ -2476,6 +2476,10 @@ def VMOVHcc  : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, pred:$p),
                RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>;
 } // hasSideEffects
 
+// The following patterns have to be defined out-of-line because the number
+// of instruction operands does not match the number of SDNode operands
+// (`pred` counts as one operand).
+
 def : Pat<(ARMcmov f64:$Dn, f64:$Dm, imm:$cc, CPSR),
           (VMOVDcc $Dn, $Dm, imm:$cc, CPSR)>,
       Requires<[HasFPRegs64]>;