Prefer 8 bits for AVR

Issue 153156

Author: tomtor

llvm/lib/Analysis/InlineCost.cpp

@@ -1766,6 +1766,9 @@ bool CallAnalyzer::visitGetElementPtr(GetElementPtrInst &I) {
 // This handles the case only when the Cmp instruction is guarding a recursive
 // call that will cause the Cmp to fail/succeed for the recursive call.
 bool CallAnalyzer::simplifyCmpInstForRecCall(CmpInst &Cmp) {
+  // FIXME Regression on AVR: github.com/llvm/llvm-project/issues/153156
+  if (!DL.isLegalInteger(32))
+    return false;
   // Bail out if LHS is not a function argument or RHS is NOT const:
   if (!isa<Argument>(Cmp.getOperand(0)) || !isa<Constant>(Cmp.getOperand(1)))
     return false;

llvm/lib/Target/AVR/AVRTargetTransformInfo.h

@@ -44,6 +44,12 @@ class AVRTTIImpl final : public BasicTTIImplBase<AVRTTIImpl> {
 
   bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
                      const TargetTransformInfo::LSRCost &C2) const override;
+
+  TypeSize
+  getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override {
+    // default is 32, so change it to 16
+    return TypeSize::getFixed(16);
+  }
 };
 
 } // end namespace llvm

llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp

@@ -1632,12 +1632,17 @@ Instruction *InstCombinerImpl::visitPHINode(PHINode &PN) {
     return replaceInstUsesWith(PN, &IdenticalPN);
   }
 
-  // If this is an integer PHI and we know that it has an illegal type, see if
+  // For 8/16 bit CPUs prefer 8 bit registers
+  bool preferByteRegister = !DL.isLegalInteger(32);
+
+  // If this is an integer PHI and we know that it has an illegal type,
+  // (or 16 bit on 8/16 bit CPUs), see if
   // it is only used by trunc or trunc(lshr) operations.  If so, we split the
   // PHI into the various pieces being extracted.  This sort of thing is
   // introduced when SROA promotes an aggregate to a single large integer type.
   if (PN.getType()->isIntegerTy() &&
-      !DL.isLegalInteger(PN.getType()->getPrimitiveSizeInBits()))
+      ((!DL.isLegalInteger(PN.getType()->getPrimitiveSizeInBits())) ||
+       (preferByteRegister && PN.getType()->getPrimitiveSizeInBits() == 16)))
     if (Instruction *Res = SliceUpIllegalIntegerPHI(PN))
       return Res;
 

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

@@ -311,6 +311,10 @@ bool InstCombinerImpl::shouldChangeType(unsigned FromWidth,
   bool FromLegal = FromWidth == 1 || DL.isLegalInteger(FromWidth);
   bool ToLegal = ToWidth == 1 || DL.isLegalInteger(ToWidth);
 
+  // For 8/16 bit CPUs prefer 8 bit.
+  if (!DL.isLegalInteger(32) && ToWidth == 16)
+    ToLegal = false;
+
   // Convert to desirable widths even if they are not legal types.
   // Only shrink types, to prevent infinite loops.
   if (ToWidth < FromWidth && isDesirableIntType(ToWidth))