[RISCV] Fix missing WriteRes for Q extensions in SiFiveP800 scheudling model

Author: mshockwave

llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td

@@ -1176,10 +1176,12 @@ foreach mx = SchedMxList in {
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedXsfvcp;
 }