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[AMDGPU] gfx1250 min/max codegen tests. NFC. (#155292)
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: smax_s64_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: smax_s64_sv
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; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MAX_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_I64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_I64_e64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_SMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smax_s64_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-LABEL: name: smax_s64_vs
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; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
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; GCN-NEXT: [[V_MAX_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_I64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_I64_e64_]]
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%0:sgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $sgpr2_sgpr3
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%2:vgpr(s64) = G_SMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smax_s64_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: smax_s64_vv
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; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MAX_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_I64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_I64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_SMAX %0, %1
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S_ENDPGM 0, implicit %2
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: smin_s64_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: smin_s64_sv
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; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MIN_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_I64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_I64_e64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_SMIN %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smin_s64_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-LABEL: name: smin_s64_vs
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; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
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; GCN-NEXT: [[V_MIN_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_I64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_I64_e64_]]
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%0:sgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $sgpr2_sgpr3
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%2:vgpr(s64) = G_SMIN %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smin_s64_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: smin_s64_vv
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; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MIN_I64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_I64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_I64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_SMIN %0, %1
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S_ENDPGM 0, implicit %2
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir‎

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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: smin_s32_ss

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: umax_s64_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: umax_s64_sv
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; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MAX_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_U64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U64_e64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_UMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: umax_s64_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-LABEL: name: umax_s64_vs
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; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
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; GCN-NEXT: [[V_MAX_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_U64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U64_e64_]]
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%0:sgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $sgpr2_sgpr3
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%2:vgpr(s64) = G_UMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: umax_s64_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: umax_s64_vv
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; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MAX_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_U64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_UMAX %0, %1
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S_ENDPGM 0, implicit %2
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: umin_s64_sv
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legalized: true
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regBankSelected: true
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9+
body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: umin_s64_sv
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; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_UMIN %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: umin_s64_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-LABEL: name: umin_s64_vs
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; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
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; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
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%0:sgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $sgpr2_sgpr3
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%2:vgpr(s64) = G_UMIN %0, %1
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S_ENDPGM 0, implicit %2
44+
...
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---
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name: umin_s64_vv
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legalized: true
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regBankSelected: true
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51+
body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: umin_s64_vv
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; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
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; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = COPY $vgpr2_vgpr3
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%2:vgpr(s64) = G_UMIN %0, %1
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S_ENDPGM 0, implicit %2
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...

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