fix test cases

Author: VyacheslavLevytskyy

llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp

@@ -1815,20 +1815,23 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
   // Query result may either be a vector or a scalar. If return type is not a
   // vector, expect only a single size component. Otherwise get the number of
   // expected components.
-  SPIRVType *RetTy = Call->ReturnType;
-  unsigned NumExpectedRetComponents = RetTy->getOpcode() == SPIRV::OpTypeVector
-                                          ? RetTy->getOperand(2).getImm()
-                                          : 1;
+  unsigned NumExpectedRetComponents =
+      Call->ReturnType->getOpcode() == SPIRV::OpTypeVector
+          ? Call->ReturnType->getOperand(2).getImm()
+          : 1;
   // Get the actual number of query result/size components.
   SPIRVType *ImgType = GR->getSPIRVTypeForVReg(Call->Arguments[0]);
   unsigned NumActualRetComponents = getNumSizeComponents(ImgType);
   Register QueryResult = Call->ReturnRegister;
   SPIRVType *QueryResultType = Call->ReturnType;
   if (NumExpectedRetComponents != NumActualRetComponents) {
+    unsigned Bitwidth = Call->ReturnType->getOpcode() == SPIRV::OpTypeInt
+                            ? Call->ReturnType->getOperand(1).getImm()
+                            : 32;
     QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister(
-        LLT::fixed_vector(NumActualRetComponents, 32));
+        LLT::fixed_vector(NumActualRetComponents, Bitwidth));
     MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::vIDRegClass);
-    SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
+    SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(Bitwidth, MIRBuilder);
     QueryResultType = GR->getOrCreateSPIRVVectorType(
         IntTy, NumActualRetComponents, MIRBuilder, true);
     GR->assignSPIRVTypeToVReg(QueryResultType, QueryResult, MIRBuilder.getMF());

llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

@@ -645,18 +645,20 @@ SPIRVGlobalRegistry::buildConstantSampler(Register ResReg, unsigned AddrMode,
       ResReg.isValid()
           ? ResReg
           : MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
-  const MachineInstr *NewMI =
-      createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
-        return MIRBuilder.buildInstr(SPIRV::OpConstantSampler)
-            .addDef(Sampler)
-            .addUse(getSPIRVTypeID(getOrCreateOpTypeSampler(MIRBuilder)))
-            .addImm(AddrMode)
-            .addImm(Param)
-            .addImm(FilerMode);
-      });
-  // TODO: this is a constant and it needs a usual control flow of add()/find()
-  // as other constants
-  return NewMI->getOperand(0).getReg();
+  SPIRVType *TypeSampler = getOrCreateOpTypeSampler(MIRBuilder);
+  Register TypeSamplerReg = getSPIRVTypeID(TypeSampler);
+  // We cannot use createOpType() logic here, because of the
+  // GlobalISel/IRTranslator.cpp check for a tail call that expects that
+  // MIRBuilder.getInsertPt() has a previous instruction. If this constant is
+  // inserted as a result of "__translate_sampler_initializer()" this would
+  // break this IRTranslator assumption.
+  MIRBuilder.buildInstr(SPIRV::OpConstantSampler)
+      .addDef(Sampler)
+      .addUse(TypeSamplerReg)
+      .addImm(AddrMode)
+      .addImm(Param)
+      .addImm(FilerMode);
+  return Sampler;
 }
 
 Register SPIRVGlobalRegistry::buildGlobalVariable(

llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

@@ -268,7 +268,8 @@ static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR,
           ToErase.push_back(AssignMI);
         MRI->replaceRegWith(Def, Source);
       } else {
-        GR->assignSPIRVTypeToVReg(AssignedPtrType, Def, MF);
+        if (!GR->getSPIRVTypeForVReg(Def, &MF))
+          GR->assignSPIRVTypeToVReg(AssignedPtrType, Def, MF);
         MIB.buildBitcast(Def, Source);
       }
     }
@@ -442,13 +443,11 @@ void insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpvType,
 
   if (!isTypeFoldingSupported(Def->getOpcode())) {
     // No need to generate SPIRV::ASSIGN_TYPE pseudo-instruction
-    if (!GR->getSPIRVTypeForVReg(Reg, &MRI.getMF())) {
-      if (!MRI.getRegClassOrNull(Reg))
-        MRI.setRegClass(Reg, GR->getRegClass(SpvType));
-      if (!MRI.getType(Reg).isValid())
-        MRI.setType(Reg, GR->getRegType(SpvType));
-      GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
-    }
+    if (!MRI.getRegClassOrNull(Reg))
+      MRI.setRegClass(Reg, GR->getRegClass(SpvType));
+    if (!MRI.getType(Reg).isValid())
+      MRI.setType(Reg, GR->getRegType(SpvType));
+    GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
     return;
   }
 

llvm/test/CodeGen/SPIRV/keep-tracked-const.ll

@@ -3,7 +3,7 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
 
-; CHECK-SPIRV-DAG: %[[#Int:]] = OpTypeInt 32 0
+; CHECK-SPIRV-DAG: %[[#Int:]] = OpTypeInt 8 0
 ; CHECK-SPIRV-DAG: %[[#C0:]] = OpConstantNull %[[#Int]]
 ; CHECK-SPIRV-DAG: %[[#C1:]] = OpConstant %[[#Int]] 1{{$}}
 

llvm/test/CodeGen/SPIRV/transcoding/OpenCL/barrier.ll

@@ -25,8 +25,8 @@
   ;; barrier(flags);
 ;; }
 
-; CHECK-SPIRV: OpName %[[#TEST_CONST_FLAGS:]] "test_barrier_const_flags"
-; CHECK-SPIRV: %[[#UINT:]] = OpTypeInt 32 0
+; CHECK-SPIRV-DAG: OpName %[[#TEST_CONST_FLAGS:]] "test_barrier_const_flags"
+; CHECK-SPIRV-DAG: %[[#UINT:]] = OpTypeInt 32 0
 
 ;; In SPIR-V, barrier is represented as OpControlBarrier [3] and OpenCL
 ;; cl_mem_fence_flags are represented as part of Memory Semantics [2], which
@@ -35,19 +35,19 @@
 ;; bit more information than original source
 
 ;; 0x10 SequentiallyConsistent + 0x100 WorkgroupMemory
-; CHECK-SPIRV:     %[[#LOCAL:]] = OpConstant %[[#UINT]] 272
+; CHECK-SPIRV-DAG: %[[#LOCAL:]] = OpConstant %[[#UINT]] 272{{$}}
 ;; 0x2 Workgroup
-; CHECK-SPIRV:     %[[#WG:]] = OpConstant %[[#UINT]] 2
+; CHECK-SPIRV-DAG: %[[#WG:]] = OpConstant %[[#UINT]] 2{{$}}
 ;; 0x10 SequentiallyConsistent + 0x200 CrossWorkgroupMemory
-; CHECK-SPIRV-DAG: %[[#GLOBAL:]] = OpConstant %[[#UINT]] 528
+; CHECK-SPIRV-DAG: %[[#GLOBAL:]] = OpConstant %[[#UINT]] 528{{$}}
 ;; 0x10 SequentiallyConsistent + 0x800 ImageMemory
-; CHECK-SPIRV-DAG: %[[#IMAGE:]] = OpConstant %[[#UINT]] 2064
+; CHECK-SPIRV-DAG: %[[#IMAGE:]] = OpConstant %[[#UINT]] 2064{{$}}
 ;; 0x10 SequentiallyConsistent + 0x100 WorkgroupMemory + 0x200 CrossWorkgroupMemory
-; CHECK-SPIRV-DAG: %[[#LOCAL_GLOBAL:]] = OpConstant %[[#UINT]] 784
+; CHECK-SPIRV-DAG: %[[#LOCAL_GLOBAL:]] = OpConstant %[[#UINT]] 784{{$}}
 ;; 0x10 SequentiallyConsistent + 0x100 WorkgroupMemory + 0x800 ImageMemory
-; CHECK-SPIRV-DAG: %[[#LOCAL_IMAGE:]] = OpConstant %[[#UINT]] 2320
+; CHECK-SPIRV-DAG: %[[#LOCAL_IMAGE:]] = OpConstant %[[#UINT]] 2320{{$}}
 ;; 0x10 SequentiallyConsistent + 0x100 WorkgroupMemory + 0x200 CrossWorkgroupMemory + 0x800 ImageMemory
-; CHECK-SPIRV-DAG: %[[#LOCAL_GLOBAL_IMAGE:]] = OpConstant %[[#UINT]] 2832
+; CHECK-SPIRV-DAG: %[[#LOCAL_GLOBAL_IMAGE:]] = OpConstant %[[#UINT]] 2832{{$}}
 
 ; CHECK-SPIRV: %[[#TEST_CONST_FLAGS]] = OpFunction %[[#]]
 ; CHECK-SPIRV: OpControlBarrier %[[#WG]] %[[#WG]] %[[#LOCAL]]