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[MC] Replace some comparisons of MCRegister and literal 0. NFC
We can convert the MCRegister to bool instead. I think this should allows us to remove MCRegister::operator==(int). All other comparisons in tree are unsigned.
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8 files changed

+48
-51
lines changed

8 files changed

+48
-51
lines changed

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 27 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1483,8 +1483,8 @@ class ARMOperand : public MCParsedAsmOperand {
14831483
if (!isGPRMem())
14841484
return false;
14851485
// No offset of any kind.
1486-
return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1487-
(alignOK || Memory.Alignment == Alignment);
1486+
return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
1487+
(alignOK || Memory.Alignment == Alignment);
14881488
}
14891489
bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
14901490
if (!isGPRMem())
@@ -1495,8 +1495,8 @@ class ARMOperand : public MCParsedAsmOperand {
14951495
return false;
14961496

14971497
// No offset of any kind.
1498-
return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1499-
(alignOK || Memory.Alignment == Alignment);
1498+
return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
1499+
(alignOK || Memory.Alignment == Alignment);
15001500
}
15011501
bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
15021502
if (!isGPRMem())
@@ -1507,8 +1507,8 @@ class ARMOperand : public MCParsedAsmOperand {
15071507
return false;
15081508

15091509
// No offset of any kind.
1510-
return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1511-
(alignOK || Memory.Alignment == Alignment);
1510+
return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
1511+
(alignOK || Memory.Alignment == Alignment);
15121512
}
15131513
bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
15141514
if (!isGPRMem())
@@ -1519,11 +1519,11 @@ class ARMOperand : public MCParsedAsmOperand {
15191519
return false;
15201520

15211521
// No offset of any kind.
1522-
return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1523-
(alignOK || Memory.Alignment == Alignment);
1522+
return !Memory.OffsetRegNum && Memory.OffsetImm == nullptr &&
1523+
(alignOK || Memory.Alignment == Alignment);
15241524
}
15251525
bool isMemPCRelImm12() const {
1526-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1526+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
15271527
return false;
15281528
// Base register must be PC.
15291529
if (Memory.BaseRegNum != ARM::PC)
@@ -1754,7 +1754,7 @@ class ARMOperand : public MCParsedAsmOperand {
17541754
}
17551755

17561756
bool isMemThumbRIs4() const {
1757-
if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1757+
if (!isGPRMem() || Memory.OffsetRegNum ||
17581758
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
17591759
return false;
17601760
// Immediate offset, multiple of 4 in range [0, 124].
@@ -1767,7 +1767,7 @@ class ARMOperand : public MCParsedAsmOperand {
17671767
}
17681768

17691769
bool isMemThumbRIs2() const {
1770-
if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1770+
if (!isGPRMem() || Memory.OffsetRegNum ||
17711771
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
17721772
return false;
17731773
// Immediate offset, multiple of 4 in range [0, 62].
@@ -1780,7 +1780,7 @@ class ARMOperand : public MCParsedAsmOperand {
17801780
}
17811781

17821782
bool isMemThumbRIs1() const {
1783-
if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1783+
if (!isGPRMem() || Memory.OffsetRegNum ||
17841784
!isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
17851785
return false;
17861786
// Immediate offset in range [0, 31].
@@ -1793,8 +1793,8 @@ class ARMOperand : public MCParsedAsmOperand {
17931793
}
17941794

17951795
bool isMemThumbSPI() const {
1796-
if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1797-
Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1796+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.BaseRegNum != ARM::SP ||
1797+
Memory.Alignment != 0)
17981798
return false;
17991799
// Immediate offset, multiple of 4 in range [0, 1020].
18001800
if (!Memory.OffsetImm) return true;
@@ -1811,7 +1811,7 @@ class ARMOperand : public MCParsedAsmOperand {
18111811
// and we reject it.
18121812
if (isImm() && !isa<MCConstantExpr>(getImm()))
18131813
return true;
1814-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1814+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
18151815
return false;
18161816
// Immediate offset a multiple of 4 in range [-1020, 1020].
18171817
if (!Memory.OffsetImm) return true;
@@ -1830,7 +1830,7 @@ class ARMOperand : public MCParsedAsmOperand {
18301830
// and we reject it.
18311831
if (isImm() && !isa<MCConstantExpr>(getImm()))
18321832
return true;
1833-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1833+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0 ||
18341834
!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
18351835
Memory.BaseRegNum))
18361836
return false;
@@ -1845,7 +1845,7 @@ class ARMOperand : public MCParsedAsmOperand {
18451845
}
18461846

18471847
bool isMemImm0_1020s4Offset() const {
1848-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1848+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
18491849
return false;
18501850
// Immediate offset a multiple of 4 in range [0, 1020].
18511851
if (!Memory.OffsetImm) return true;
@@ -1857,7 +1857,7 @@ class ARMOperand : public MCParsedAsmOperand {
18571857
}
18581858

18591859
bool isMemImm8Offset() const {
1860-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1860+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
18611861
return false;
18621862
// Base reg of PC isn't allowed for these encodings.
18631863
if (Memory.BaseRegNum == ARM::PC) return false;
@@ -1873,7 +1873,7 @@ class ARMOperand : public MCParsedAsmOperand {
18731873

18741874
template<unsigned Bits, unsigned RegClassID>
18751875
bool isMemImm7ShiftedOffset() const {
1876-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1876+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0 ||
18771877
!ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
18781878
return false;
18791879

@@ -1924,7 +1924,7 @@ class ARMOperand : public MCParsedAsmOperand {
19241924
}
19251925

19261926
template <int shift> bool isMemRegQOffset() const {
1927-
if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1927+
if (!isMVEMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
19281928
return false;
19291929

19301930
if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
@@ -1952,7 +1952,7 @@ class ARMOperand : public MCParsedAsmOperand {
19521952
}
19531953

19541954
bool isMemPosImm8Offset() const {
1955-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1955+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
19561956
return false;
19571957
// Immediate offset in range [0, 255].
19581958
if (!Memory.OffsetImm) return true;
@@ -1964,7 +1964,7 @@ class ARMOperand : public MCParsedAsmOperand {
19641964
}
19651965

19661966
bool isMemNegImm8Offset() const {
1967-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1967+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
19681968
return false;
19691969
// Base reg of PC isn't allowed for these encodings.
19701970
if (Memory.BaseRegNum == ARM::PC) return false;
@@ -1979,7 +1979,7 @@ class ARMOperand : public MCParsedAsmOperand {
19791979
}
19801980

19811981
bool isMemUImm12Offset() const {
1982-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1982+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
19831983
return false;
19841984
// Immediate offset in range [0, 4095].
19851985
if (!Memory.OffsetImm) return true;
@@ -1998,7 +1998,7 @@ class ARMOperand : public MCParsedAsmOperand {
19981998
if (isImm() && !isa<MCConstantExpr>(getImm()))
19991999
return true;
20002000

2001-
if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
2001+
if (!isGPRMem() || Memory.OffsetRegNum || Memory.Alignment != 0)
20022002
return false;
20032003
// Immediate offset in range [-4095, 4095].
20042004
if (!Memory.OffsetImm) return true;
@@ -8982,8 +8982,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
89828982
}
89838983
// Alias for alternate form of 'ADR Rd, #imm' instruction.
89848984
case ARM::ADDri: {
8985-
if (Inst.getOperand(1).getReg() != ARM::PC ||
8986-
Inst.getOperand(5).getReg() != 0 ||
8985+
if (Inst.getOperand(1).getReg() != ARM::PC || Inst.getOperand(5).getReg() ||
89878986
!(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
89888987
return false;
89898988
MCInst TmpInst;
@@ -10703,7 +10702,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1070310702
case ARM::t2ADDspImm:
1070410703
case ARM::t2SUBspImm: {
1070510704
// Prefer T1 encoding if possible
10706-
if (Inst.getOperand(5).getReg() != 0 || HasWideQualifier)
10705+
if (Inst.getOperand(5).getReg() || HasWideQualifier)
1070710706
break;
1070810707
unsigned V = Inst.getOperand(2).getImm();
1070910708
if (V & 3 || V > ((1 << 7) - 1) << 2)
@@ -10732,9 +10731,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
1073210731
Transform = true;
1073310732
Swap = true;
1073410733
}
10735-
if (!Transform ||
10736-
Inst.getOperand(5).getReg() != 0 ||
10737-
HasWideQualifier)
10734+
if (!Transform || Inst.getOperand(5).getReg() || HasWideQualifier)
1073810735
break;
1073910736
MCInst TmpInst;
1074010737
TmpInst.setOpcode(ARM::tADDhirr);

‎llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -767,7 +767,7 @@ void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
767767
const MCSubtargetInfo &STI,
768768
raw_ostream &O) {
769769
const MCOperand &MO = MI->getOperand(OpNum);
770-
if (MO.getReg() == 0)
770+
if (!MO.getReg())
771771
O << "!";
772772
else {
773773
O << ", ";

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1356,7 +1356,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
13561356
// the register from VR to VRM2/VRM4/VRM8 if necessary.
13571357
if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
13581358
Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
1359-
if (Op.Reg.RegNum == 0)
1359+
if (!Op.Reg.RegNum)
13601360
return Match_InvalidOperand;
13611361
return Match_Success;
13621362
}

‎llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1399,14 +1399,14 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
13991399
RegNo = MatchRegisterName(RegName);
14001400

14011401
// If the match failed, try the register name as lowercase.
1402-
if (RegNo == 0)
1402+
if (!RegNo)
14031403
RegNo = MatchRegisterName(RegName.lower());
14041404

14051405
// The "flags" and "mxcsr" registers cannot be referenced directly.
14061406
// Treat it as an identifier instead.
14071407
if (isParsingMSInlineAsm() && isParsingIntelSyntax() &&
14081408
(RegNo == X86::EFLAGS || RegNo == X86::MXCSR))
1409-
RegNo = 0;
1409+
RegNo = MCRegister();
14101410

14111411
if (!is64BitMode()) {
14121412
// FIXME: This should be done using Requires<Not64BitMode> and
@@ -1427,7 +1427,7 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
14271427

14281428
// If this is "db[0-15]", match it as an alias
14291429
// for dr[0-15].
1430-
if (RegNo == 0 && RegName.starts_with("db")) {
1430+
if (!RegNo && RegName.starts_with("db")) {
14311431
if (RegName.size() == 3) {
14321432
switch (RegName[2]) {
14331433
case '0':
@@ -1485,7 +1485,7 @@ bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
14851485
}
14861486
}
14871487

1488-
if (RegNo == 0) {
1488+
if (!RegNo) {
14891489
if (isParsingIntelSyntax())
14901490
return true;
14911491
return Error(StartLoc, "invalid register name", SMRange(StartLoc, EndLoc));
@@ -1497,7 +1497,7 @@ bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
14971497
SMLoc &EndLoc, bool RestoreOnFailure) {
14981498
MCAsmParser &Parser = getParser();
14991499
MCAsmLexer &Lexer = getLexer();
1500-
RegNo = 0;
1500+
RegNo = MCRegister();
15011501

15021502
SmallVector<AsmToken, 5> Tokens;
15031503
auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() {
@@ -1579,7 +1579,7 @@ bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
15791579

15801580
EndLoc = Parser.getTok().getEndLoc();
15811581

1582-
if (RegNo == 0) {
1582+
if (!RegNo) {
15831583
OnFailure();
15841584
if (isParsingIntelSyntax()) return true;
15851585
return Error(StartLoc, "invalid register name",
@@ -3030,7 +3030,7 @@ bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp,
30303030
// base-index-scale-expr.
30313031

30323032
if (!parseOptionalToken(AsmToken::LParen)) {
3033-
if (SegReg == 0)
3033+
if (!SegReg)
30343034
Operands.push_back(
30353035
X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc));
30363036
else
@@ -3119,7 +3119,7 @@ bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp,
31193119
// This is to support otherwise illegal operand (%dx) found in various
31203120
// unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
31213121
// be supported. Mark such DX variants separately fix only in special cases.
3122-
if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
3122+
if (BaseReg == X86::DX && !IndexReg && Scale == 1 && !SegReg &&
31233123
isa<MCConstantExpr>(Disp) &&
31243124
cast<MCConstantExpr>(Disp)->getValue() == 0) {
31253125
Operands.push_back(X86Operand::CreateDXReg(BaseLoc, BaseLoc));
@@ -4920,14 +4920,14 @@ bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
49204920

49214921
// The SEH register number is the same as the encoding register number. Map
49224922
// from the encoding back to the LLVM register number.
4923-
RegNo = 0;
4923+
RegNo = MCRegister();
49244924
for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
49254925
if (MRI->getEncodingValue(Reg) == EncodedReg) {
49264926
RegNo = Reg;
49274927
break;
49284928
}
49294929
}
4930-
if (RegNo == 0) {
4930+
if (!RegNo) {
49314931
return Error(startLoc,
49324932
"incorrect register number for use with this directive");
49334933
}

‎llvm/lib/Target/X86/AsmParser/X86Operand.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -451,10 +451,11 @@ struct X86Operand final : public MCParsedAsmOperand {
451451

452452
bool isDstIdx() const {
453453
return !getMemIndexReg() && getMemScale() == 1 &&
454-
(getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
455-
(getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
456-
getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
457-
cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
454+
(!getMemSegReg() || getMemSegReg() == X86::ES) &&
455+
(getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
456+
getMemBaseReg() == X86::DI) &&
457+
isa<MCConstantExpr>(getMemDisp()) &&
458+
cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
458459
}
459460
bool isDstIdx8() const {
460461
return isMem8() && isDstIdx();

‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -330,7 +330,7 @@ uint8_t X86AsmBackend::determinePaddingPrefix(const MCInst &Inst) const {
330330
}
331331
}
332332

333-
if (SegmentReg != 0)
333+
if (SegmentReg)
334334
return X86::getSegmentOverridePrefixForReg(SegmentReg);
335335

336336
if (STI.hasFeature(X86::Is64Bit))

‎llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -377,9 +377,9 @@ bool X86::optimizeMOV(MCInst &MI, bool In64BitMode) {
377377
if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
378378
Absolute = false;
379379
}
380-
if (Absolute && (MI.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
380+
if (Absolute && (MI.getOperand(AddrBase + X86::AddrBaseReg).getReg() ||
381381
MI.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
382-
MI.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
382+
MI.getOperand(AddrBase + X86::AddrIndexReg).getReg()))
383383
return false;
384384
// If so, rewrite the instruction.
385385
MCOperand Saved = MI.getOperand(AddrOp);

‎llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -621,8 +621,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
621621
BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
622622
assert(STI.hasFeature(X86::Is64Bit) &&
623623
"Rip-relative addressing requires 64-bit mode");
624-
assert(IndexReg.getReg() == 0 && !ForceSIB &&
625-
"Invalid rip-relative address");
624+
assert(!IndexReg.getReg() && !ForceSIB && "Invalid rip-relative address");
626625
emitByte(modRMByte(0, RegOpcodeField, 5), CB);
627626

628627
unsigned Opcode = MI.getOpcode();

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