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[RISCV] Ensure the valid vtype during whole RVVReg move
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174 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -421,6 +421,36 @@ void RISCVInstrInfo::copyPhysRegVector(
421421
auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), ActualDstReg);
422422
bool UseVMV_V_I = RISCV::getRVVMCOpcode(Opc) == RISCV::VMV_V_I;
423423
bool UseVMV = UseVMV_V_I || RISCV::getRVVMCOpcode(Opc) == RISCV::VMV_V_V;
424+
425+
// Address https://github.com/llvm/llvm-project/issues/114518
426+
// Make sure each whole RVVReg move has valid vtype.
427+
unsigned Opcode = MIB->getOpcode();
428+
if (UseVMV || Opcode == RISCV::VMV1R_V || Opcode == RISCV::VMV2R_V ||
429+
Opcode == RISCV::VMV4R_V || Opcode == RISCV::VMV8R_V) {
430+
431+
// TODO: Data-flow analysis for vtype status could help avoid the
432+
// redundant one.
433+
bool NeedVSETIVLI = true;
434+
435+
for (auto &CurrMI : MBB) {
436+
unsigned CurrMIOpcode = CurrMI.getOpcode();
437+
if (CurrMIOpcode == RISCV::PseudoVSETIVLI ||
438+
CurrMIOpcode == RISCV::PseudoVSETVLI ||
439+
CurrMIOpcode == RISCV::PseudoVSETVLIX0)
440+
NeedVSETIVLI = false;
441+
else if (CurrMI.isInlineAsm())
442+
NeedVSETIVLI = true;
443+
else if (NeedVSETIVLI && CurrMI.isIdenticalTo(*MIB)) {
444+
BuildMI(MBB, &*MIB, MIB->getDebugLoc(), get(RISCV::PseudoVSETIVLI))
445+
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
446+
.addImm(0)
447+
.addImm(RISCVVType::encodeVTYPE(RISCVII::VLMUL::LMUL_1, 32, false,
448+
false));
449+
break;
450+
}
451+
}
452+
}
453+
424454
if (UseVMV)
425455
MIB.addReg(ActualDstReg, RegState::Undef);
426456
if (UseVMV_V_I)

‎llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@ define <vscale x 1 x i8> @constraint_vd(<vscale x 1 x i8> %0, <vscale x 1 x i8>
4545
define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
4646
; RV32I-LABEL: constraint_vm:
4747
; RV32I: # %bb.0:
48+
; RV32I-NEXT: vsetivli zero, 0, e32, m1, tu, mu
4849
; RV32I-NEXT: vmv1r.v v9, v0
4950
; RV32I-NEXT: vmv1r.v v0, v8
5051
; RV32I-NEXT: #APP
@@ -54,6 +55,7 @@ define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1>
5455
;
5556
; RV64I-LABEL: constraint_vm:
5657
; RV64I: # %bb.0:
58+
; RV64I-NEXT: vsetivli zero, 0, e32, m1, tu, mu
5759
; RV64I-NEXT: vmv1r.v v9, v0
5860
; RV64I-NEXT: vmv1r.v v0, v8
5961
; RV64I-NEXT: #APP

‎llvm/test/CodeGen/RISCV/rvv/abs-vp.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -567,6 +567,7 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
567567
; CHECK-NEXT: slli a1, a1, 4
568568
; CHECK-NEXT: sub sp, sp, a1
569569
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
570+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
570571
; CHECK-NEXT: vmv1r.v v24, v0
571572
; CHECK-NEXT: csrr a1, vlenb
572573
; CHECK-NEXT: slli a1, a1, 3
@@ -590,6 +591,7 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
590591
; CHECK-NEXT: # %bb.1:
591592
; CHECK-NEXT: mv a0, a1
592593
; CHECK-NEXT: .LBB46_2:
594+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
593595
; CHECK-NEXT: vmv1r.v v0, v24
594596
; CHECK-NEXT: slli a1, a1, 3
595597
; CHECK-NEXT: add a1, sp, a1

‎llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3075,6 +3075,7 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
30753075
; CHECK-NEXT: slli a1, a1, 4
30763076
; CHECK-NEXT: sub sp, sp, a1
30773077
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
3078+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
30783079
; CHECK-NEXT: vmv1r.v v24, v0
30793080
; CHECK-NEXT: csrr a1, vlenb
30803081
; CHECK-NEXT: slli a1, a1, 3
@@ -3121,6 +3122,7 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
31213122
; CHECK-NEXT: # %bb.1:
31223123
; CHECK-NEXT: mv a0, a3
31233124
; CHECK-NEXT: .LBB46_2:
3125+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
31243126
; CHECK-NEXT: vmv1r.v v0, v24
31253127
; CHECK-NEXT: csrr a3, vlenb
31263128
; CHECK-NEXT: slli a3, a3, 3
@@ -3158,6 +3160,7 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
31583160
;
31593161
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:
31603162
; CHECK-ZVBB: # %bb.0:
3163+
; CHECK-ZVBB-NEXT: vsetivli zero, 0, e32, m1, tu, mu
31613164
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
31623165
; CHECK-ZVBB-NEXT: csrr a1, vlenb
31633166
; CHECK-ZVBB-NEXT: srli a2, a1, 1
@@ -3174,6 +3177,7 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
31743177
; CHECK-ZVBB-NEXT: # %bb.1:
31753178
; CHECK-ZVBB-NEXT: mv a0, a1
31763179
; CHECK-ZVBB-NEXT: .LBB46_2:
3180+
; CHECK-ZVBB-NEXT: vsetivli zero, 0, e32, m1, tu, mu
31773181
; CHECK-ZVBB-NEXT: vmv1r.v v0, v24
31783182
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
31793183
; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t

‎llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1584,6 +1584,7 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
15841584
; CHECK-NEXT: slli a1, a1, 4
15851585
; CHECK-NEXT: sub sp, sp, a1
15861586
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
1587+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
15871588
; CHECK-NEXT: vmv1r.v v24, v0
15881589
; CHECK-NEXT: csrr a1, vlenb
15891590
; CHECK-NEXT: slli a1, a1, 3
@@ -1609,6 +1610,7 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
16091610
; CHECK-NEXT: # %bb.1:
16101611
; CHECK-NEXT: mv a0, a1
16111612
; CHECK-NEXT: .LBB32_2:
1613+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
16121614
; CHECK-NEXT: vmv1r.v v0, v24
16131615
; CHECK-NEXT: csrr a1, vlenb
16141616
; CHECK-NEXT: slli a1, a1, 3
@@ -1631,6 +1633,7 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
16311633
;
16321634
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:
16331635
; CHECK-ZVKB: # %bb.0:
1636+
; CHECK-ZVKB-NEXT: vsetivli zero, 0, e32, m1, tu, mu
16341637
; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
16351638
; CHECK-ZVKB-NEXT: csrr a1, vlenb
16361639
; CHECK-ZVKB-NEXT: srli a2, a1, 1
@@ -1647,6 +1650,7 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
16471650
; CHECK-ZVKB-NEXT: # %bb.1:
16481651
; CHECK-ZVKB-NEXT: mv a0, a1
16491652
; CHECK-ZVKB-NEXT: .LBB32_2:
1653+
; CHECK-ZVKB-NEXT: vsetivli zero, 0, e32, m1, tu, mu
16501654
; CHECK-ZVKB-NEXT: vmv1r.v v0, v24
16511655
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
16521656
; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t

‎llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -336,6 +336,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vsca
336336
; RV32-NEXT: add a1, a3, a1
337337
; RV32-NEXT: li a3, 2
338338
; RV32-NEXT: vs8r.v v16, (a1)
339+
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
339340
; RV32-NEXT: vmv8r.v v8, v0
340341
; RV32-NEXT: vmv8r.v v16, v24
341342
; RV32-NEXT: call ext2
@@ -374,6 +375,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vsca
374375
; RV64-NEXT: add a1, a3, a1
375376
; RV64-NEXT: li a3, 2
376377
; RV64-NEXT: vs8r.v v16, (a1)
378+
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
377379
; RV64-NEXT: vmv8r.v v8, v0
378380
; RV64-NEXT: vmv8r.v v16, v24
379381
; RV64-NEXT: call ext2
@@ -451,6 +453,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_
451453
; RV32-NEXT: add a1, sp, a1
452454
; RV32-NEXT: addi a1, a1, 128
453455
; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
456+
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
454457
; RV32-NEXT: vmv8r.v v16, v0
455458
; RV32-NEXT: call ext3
456459
; RV32-NEXT: addi sp, s0, -144
@@ -523,6 +526,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_
523526
; RV64-NEXT: add a1, sp, a1
524527
; RV64-NEXT: addi a1, a1, 128
525528
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
529+
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
526530
; RV64-NEXT: vmv8r.v v16, v0
527531
; RV64-NEXT: call ext3
528532
; RV64-NEXT: addi sp, s0, -144

‎llvm/test/CodeGen/RISCV/rvv/calling-conv.ll‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@ define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @caller_tuple_return(
103103
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
104104
; RV32-NEXT: .cfi_offset ra, -4
105105
; RV32-NEXT: call callee_tuple_return
106+
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
106107
; RV32-NEXT: vmv2r.v v6, v8
107108
; RV32-NEXT: vmv2r.v v8, v10
108109
; RV32-NEXT: vmv2r.v v10, v6
@@ -119,6 +120,7 @@ define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @caller_tuple_return(
119120
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
120121
; RV64-NEXT: .cfi_offset ra, -8
121122
; RV64-NEXT: call callee_tuple_return
123+
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
122124
; RV64-NEXT: vmv2r.v v6, v8
123125
; RV64-NEXT: vmv2r.v v8, v10
124126
; RV64-NEXT: vmv2r.v v10, v6
@@ -144,6 +146,7 @@ define void @caller_tuple_argument(target("riscv.vector.tuple", <vscale x 16 x i
144146
; RV32-NEXT: .cfi_def_cfa_offset 16
145147
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
146148
; RV32-NEXT: .cfi_offset ra, -4
149+
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
147150
; RV32-NEXT: vmv2r.v v6, v8
148151
; RV32-NEXT: vmv2r.v v8, v10
149152
; RV32-NEXT: vmv2r.v v10, v6
@@ -160,6 +163,7 @@ define void @caller_tuple_argument(target("riscv.vector.tuple", <vscale x 16 x i
160163
; RV64-NEXT: .cfi_def_cfa_offset 16
161164
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
162165
; RV64-NEXT: .cfi_offset ra, -8
166+
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
163167
; RV64-NEXT: vmv2r.v v6, v8
164168
; RV64-NEXT: vmv2r.v v8, v10
165169
; RV64-NEXT: vmv2r.v v10, v6

‎llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,7 @@ declare <vscale x 4 x bfloat> @llvm.vp.ceil.nxv4bf16(<vscale x 4 x bfloat>, <vsc
117117
define <vscale x 4 x bfloat> @vp_ceil_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
118118
; CHECK-LABEL: vp_ceil_vv_nxv4bf16:
119119
; CHECK: # %bb.0:
120+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
120121
; CHECK-NEXT: vmv1r.v v9, v0
121122
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
122123
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
@@ -169,6 +170,7 @@ declare <vscale x 8 x bfloat> @llvm.vp.ceil.nxv8bf16(<vscale x 8 x bfloat>, <vsc
169170
define <vscale x 8 x bfloat> @vp_ceil_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
170171
; CHECK-LABEL: vp_ceil_vv_nxv8bf16:
171172
; CHECK: # %bb.0:
173+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
172174
; CHECK-NEXT: vmv1r.v v10, v0
173175
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
174176
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
@@ -221,6 +223,7 @@ declare <vscale x 16 x bfloat> @llvm.vp.ceil.nxv16bf16(<vscale x 16 x bfloat>, <
221223
define <vscale x 16 x bfloat> @vp_ceil_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
222224
; CHECK-LABEL: vp_ceil_vv_nxv16bf16:
223225
; CHECK: # %bb.0:
226+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
224227
; CHECK-NEXT: vmv1r.v v12, v0
225228
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
226229
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
@@ -279,6 +282,7 @@ define <vscale x 32 x bfloat> @vp_ceil_vv_nxv32bf16(<vscale x 32 x bfloat> %va,
279282
; CHECK-NEXT: slli a1, a1, 3
280283
; CHECK-NEXT: sub sp, sp, a1
281284
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
285+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
282286
; CHECK-NEXT: vmv1r.v v7, v0
283287
; CHECK-NEXT: csrr a2, vlenb
284288
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
@@ -317,6 +321,7 @@ define <vscale x 32 x bfloat> @vp_ceil_vv_nxv32bf16(<vscale x 32 x bfloat> %va,
317321
; CHECK-NEXT: mv a0, a1
318322
; CHECK-NEXT: .LBB10_2:
319323
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
324+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
320325
; CHECK-NEXT: vmv1r.v v0, v7
321326
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
322327
; CHECK-NEXT: vfabs.v v16, v24, v0.t
@@ -582,6 +587,7 @@ define <vscale x 4 x half> @vp_ceil_vv_nxv4f16(<vscale x 4 x half> %va, <vscale
582587
;
583588
; ZVFHMIN-LABEL: vp_ceil_vv_nxv4f16:
584589
; ZVFHMIN: # %bb.0:
590+
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
585591
; ZVFHMIN-NEXT: vmv1r.v v9, v0
586592
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
587593
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -649,6 +655,7 @@ declare <vscale x 8 x half> @llvm.vp.ceil.nxv8f16(<vscale x 8 x half>, <vscale x
649655
define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
650656
; ZVFH-LABEL: vp_ceil_vv_nxv8f16:
651657
; ZVFH: # %bb.0:
658+
; ZVFH-NEXT: vsetivli zero, 0, e32, m1, tu, mu
652659
; ZVFH-NEXT: vmv1r.v v10, v0
653660
; ZVFH-NEXT: lui a1, %hi(.LCPI18_0)
654661
; ZVFH-NEXT: flh fa5, %lo(.LCPI18_0)(a1)
@@ -668,6 +675,7 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale
668675
;
669676
; ZVFHMIN-LABEL: vp_ceil_vv_nxv8f16:
670677
; ZVFHMIN: # %bb.0:
678+
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
671679
; ZVFHMIN-NEXT: vmv1r.v v10, v0
672680
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
673681
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -735,6 +743,7 @@ declare <vscale x 16 x half> @llvm.vp.ceil.nxv16f16(<vscale x 16 x half>, <vscal
735743
define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
736744
; ZVFH-LABEL: vp_ceil_vv_nxv16f16:
737745
; ZVFH: # %bb.0:
746+
; ZVFH-NEXT: vsetivli zero, 0, e32, m1, tu, mu
738747
; ZVFH-NEXT: vmv1r.v v12, v0
739748
; ZVFH-NEXT: lui a1, %hi(.LCPI20_0)
740749
; ZVFH-NEXT: flh fa5, %lo(.LCPI20_0)(a1)
@@ -754,6 +763,7 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
754763
;
755764
; ZVFHMIN-LABEL: vp_ceil_vv_nxv16f16:
756765
; ZVFHMIN: # %bb.0:
766+
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
757767
; ZVFHMIN-NEXT: vmv1r.v v12, v0
758768
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
759769
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
@@ -821,6 +831,7 @@ declare <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half>, <vscal
821831
define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
822832
; ZVFH-LABEL: vp_ceil_vv_nxv32f16:
823833
; ZVFH: # %bb.0:
834+
; ZVFH-NEXT: vsetivli zero, 0, e32, m1, tu, mu
824835
; ZVFH-NEXT: vmv1r.v v16, v0
825836
; ZVFH-NEXT: lui a1, %hi(.LCPI22_0)
826837
; ZVFH-NEXT: flh fa5, %lo(.LCPI22_0)(a1)
@@ -846,6 +857,7 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
846857
; ZVFHMIN-NEXT: slli a1, a1, 3
847858
; ZVFHMIN-NEXT: sub sp, sp, a1
848859
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
860+
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
849861
; ZVFHMIN-NEXT: vmv1r.v v7, v0
850862
; ZVFHMIN-NEXT: csrr a2, vlenb
851863
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
@@ -884,6 +896,7 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
884896
; ZVFHMIN-NEXT: mv a0, a1
885897
; ZVFHMIN-NEXT: .LBB22_2:
886898
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
899+
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
887900
; ZVFHMIN-NEXT: vmv1r.v v0, v7
888901
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
889902
; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
@@ -1068,6 +1081,7 @@ declare <vscale x 4 x float> @llvm.vp.ceil.nxv4f32(<vscale x 4 x float>, <vscale
10681081
define <vscale x 4 x float> @vp_ceil_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
10691082
; CHECK-LABEL: vp_ceil_vv_nxv4f32:
10701083
; CHECK: # %bb.0:
1084+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
10711085
; CHECK-NEXT: vmv1r.v v10, v0
10721086
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
10731087
; CHECK-NEXT: vfabs.v v12, v8, v0.t
@@ -1112,6 +1126,7 @@ declare <vscale x 8 x float> @llvm.vp.ceil.nxv8f32(<vscale x 8 x float>, <vscale
11121126
define <vscale x 8 x float> @vp_ceil_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
11131127
; CHECK-LABEL: vp_ceil_vv_nxv8f32:
11141128
; CHECK: # %bb.0:
1129+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
11151130
; CHECK-NEXT: vmv1r.v v12, v0
11161131
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
11171132
; CHECK-NEXT: vfabs.v v16, v8, v0.t
@@ -1156,6 +1171,7 @@ declare <vscale x 16 x float> @llvm.vp.ceil.nxv16f32(<vscale x 16 x float>, <vsc
11561171
define <vscale x 16 x float> @vp_ceil_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
11571172
; CHECK-LABEL: vp_ceil_vv_nxv16f32:
11581173
; CHECK: # %bb.0:
1174+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
11591175
; CHECK-NEXT: vmv1r.v v16, v0
11601176
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
11611177
; CHECK-NEXT: vfabs.v v24, v8, v0.t
@@ -1242,6 +1258,7 @@ declare <vscale x 2 x double> @llvm.vp.ceil.nxv2f64(<vscale x 2 x double>, <vsca
12421258
define <vscale x 2 x double> @vp_ceil_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
12431259
; CHECK-LABEL: vp_ceil_vv_nxv2f64:
12441260
; CHECK: # %bb.0:
1261+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
12451262
; CHECK-NEXT: vmv1r.v v10, v0
12461263
; CHECK-NEXT: lui a1, %hi(.LCPI36_0)
12471264
; CHECK-NEXT: fld fa5, %lo(.LCPI36_0)(a1)
@@ -1286,6 +1303,7 @@ declare <vscale x 4 x double> @llvm.vp.ceil.nxv4f64(<vscale x 4 x double>, <vsca
12861303
define <vscale x 4 x double> @vp_ceil_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
12871304
; CHECK-LABEL: vp_ceil_vv_nxv4f64:
12881305
; CHECK: # %bb.0:
1306+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
12891307
; CHECK-NEXT: vmv1r.v v12, v0
12901308
; CHECK-NEXT: lui a1, %hi(.LCPI38_0)
12911309
; CHECK-NEXT: fld fa5, %lo(.LCPI38_0)(a1)
@@ -1330,6 +1348,7 @@ declare <vscale x 7 x double> @llvm.vp.ceil.nxv7f64(<vscale x 7 x double>, <vsca
13301348
define <vscale x 7 x double> @vp_ceil_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
13311349
; CHECK-LABEL: vp_ceil_vv_nxv7f64:
13321350
; CHECK: # %bb.0:
1351+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
13331352
; CHECK-NEXT: vmv1r.v v16, v0
13341353
; CHECK-NEXT: lui a1, %hi(.LCPI40_0)
13351354
; CHECK-NEXT: fld fa5, %lo(.LCPI40_0)(a1)
@@ -1374,6 +1393,7 @@ declare <vscale x 8 x double> @llvm.vp.ceil.nxv8f64(<vscale x 8 x double>, <vsca
13741393
define <vscale x 8 x double> @vp_ceil_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
13751394
; CHECK-LABEL: vp_ceil_vv_nxv8f64:
13761395
; CHECK: # %bb.0:
1396+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
13771397
; CHECK-NEXT: vmv1r.v v16, v0
13781398
; CHECK-NEXT: lui a1, %hi(.LCPI42_0)
13791399
; CHECK-NEXT: fld fa5, %lo(.LCPI42_0)(a1)
@@ -1425,6 +1445,7 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
14251445
; CHECK-NEXT: slli a1, a1, 3
14261446
; CHECK-NEXT: sub sp, sp, a1
14271447
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
1448+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
14281449
; CHECK-NEXT: vmv1r.v v7, v0
14291450
; CHECK-NEXT: csrr a1, vlenb
14301451
; CHECK-NEXT: lui a2, %hi(.LCPI44_0)
@@ -1458,6 +1479,7 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
14581479
; CHECK-NEXT: # %bb.1:
14591480
; CHECK-NEXT: mv a0, a1
14601481
; CHECK-NEXT: .LBB44_2:
1482+
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
14611483
; CHECK-NEXT: vmv1r.v v0, v7
14621484
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
14631485
; CHECK-NEXT: vfabs.v v16, v8, v0.t

‎llvm/test/CodeGen/RISCV/rvv/compressstore.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,7 @@ entry:
197197
define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data) {
198198
; RV64-LABEL: test_compresstore_v256i8:
199199
; RV64: # %bb.0: # %entry
200+
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
200201
; RV64-NEXT: vmv1r.v v7, v8
201202
; RV64-NEXT: li a2, 128
202203
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -230,6 +231,7 @@ define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data
230231
; RV32-NEXT: slli a2, a2, 3
231232
; RV32-NEXT: sub sp, sp, a2
232233
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
234+
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
233235
; RV32-NEXT: vmv8r.v v24, v16
234236
; RV32-NEXT: li a2, 128
235237
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma

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