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[PowerPC] Fix instruction name for dmr insert (#134301)
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12 files changed

+109
-109
lines changed

12 files changed

+109
-109
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11814,11 +11814,11 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
1181411814
}
1181511815

1181611816
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
11817-
SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTFDMR512, dl, MVT::v512i1, Loads[0],
11817+
SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Loads[0],
1181811818
Loads[1]),
1181911819
0);
1182011820
SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
11821-
SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTFDMR512_HI, dl, MVT::v512i1,
11821+
SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
1182211822
Loads[2], Loads[3]),
1182311823
0);
1182411824
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);

‎llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -174,25 +174,25 @@ let Predicates = [IsISAFuture] in {
174174
let P = 1;
175175
}
176176

177-
def DMXXINSTFDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
177+
def DMXXINSTDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
178178
(ins vsrprc:$XAp, vsrprc:$XBp),
179-
"dmxxinstfdmr512 $AT, $XAp, $XBp, 0", []> {
179+
"dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> {
180180
let P = 0;
181181
}
182182

183-
def DMXXINSTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
183+
def DMXXINSTDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
184184
(ins vsrprc:$XAp, vsrprc:$XBp),
185-
"dmxxinstfdmr512 $AT, $XAp, $XBp, 1", []> {
185+
"dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> {
186186
let P = 1;
187187
}
188188

189189
def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
190190
(ins dmrrowp:$AT, u2imm:$P),
191191
"dmxxextfdmr256 $XBp, $AT, $P", []>;
192192

193-
def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
193+
def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
194194
(ins vsrprc:$XBp, u2imm:$P),
195-
"dmxxinstfdmr256 $AT, $XBp, $P", []>;
195+
"dmxxinstdmr256 $AT, $XBp, $P", []>;
196196

197197
def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
198198
"dmmr $AT, $AB",

‎llvm/lib/Target/PowerPC/PPCInstrMMA.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1089,9 +1089,9 @@ let Predicates = [MMA, IsNotISAFuture] in {
10891089

10901090
let Predicates = [MMA, IsISAFuture] in {
10911091
def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1092-
(DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
1092+
(DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
10931093
def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
10941094
v16i8:$vs3, v16i8:$vs2)),
1095-
(DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
1095+
(DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
10961096
def : Pat<(v512i1 immAllZerosV), (XXSETACCZW)>;
10971097
}

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1448,7 +1448,7 @@ void PPCRegisterInfo::lowerWACCRestore(MachineBasicBlock::iterator II,
14481448
FrameIndex, IsLittleEndian ? 0 : 32);
14491449

14501450
// Kill VSRpReg0, VSRpReg1 (killedRegState::Killed)
1451-
BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTFDMR512), DestReg)
1451+
BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTDMR512), DestReg)
14521452
.addReg(VSRpReg0, RegState::Kill)
14531453
.addReg(VSRpReg1, RegState::Kill);
14541454

‎llvm/test/CodeGen/PowerPC/dmf-outer-product.ll‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
5151
; CHECK: # %bb.0: # %entry
5252
; CHECK-NEXT: lxvp vsp34, 0(r3)
5353
; CHECK-NEXT: lxvp vsp36, 32(r3)
54-
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
54+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
5555
; CHECK-NEXT: lxvp vsp34, 64(r3)
5656
; CHECK-NEXT: lxvp vsp36, 96(r3)
57-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
57+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
5858
; CHECK-NEXT: lxv v2, 16(r4)
5959
; CHECK-NEXT: lxv vs0, 0(r5)
6060
; CHECK-NEXT: lxv v3, 0(r4)
@@ -71,10 +71,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
7171
; CHECK-BE: # %bb.0: # %entry
7272
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
7373
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
74-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
74+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
7575
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
7676
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
77-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
77+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
7878
; CHECK-BE-NEXT: lxv v2, 0(r4)
7979
; CHECK-BE-NEXT: lxv vs0, 0(r5)
8080
; CHECK-BE-NEXT: lxv v3, 16(r4)
@@ -102,10 +102,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
102102
; CHECK: # %bb.0: # %entry
103103
; CHECK-NEXT: lxvp vsp34, 0(r3)
104104
; CHECK-NEXT: lxvp vsp36, 32(r3)
105-
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
105+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
106106
; CHECK-NEXT: lxvp vsp34, 64(r3)
107107
; CHECK-NEXT: lxvp vsp36, 96(r3)
108-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
108+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
109109
; CHECK-NEXT: lxv v2, 16(r4)
110110
; CHECK-NEXT: lxv vs0, 0(r5)
111111
; CHECK-NEXT: lxv v3, 0(r4)
@@ -122,10 +122,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
122122
; CHECK-BE: # %bb.0: # %entry
123123
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
124124
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
125-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
125+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
126126
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
127127
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
128-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
128+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
129129
; CHECK-BE-NEXT: lxv v2, 0(r4)
130130
; CHECK-BE-NEXT: lxv vs0, 0(r5)
131131
; CHECK-BE-NEXT: lxv v3, 16(r4)
@@ -153,10 +153,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
153153
; CHECK: # %bb.0: # %entry
154154
; CHECK-NEXT: lxvp vsp34, 0(r3)
155155
; CHECK-NEXT: lxvp vsp36, 32(r3)
156-
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
156+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
157157
; CHECK-NEXT: lxvp vsp34, 64(r3)
158158
; CHECK-NEXT: lxvp vsp36, 96(r3)
159-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
159+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
160160
; CHECK-NEXT: lxv v2, 16(r4)
161161
; CHECK-NEXT: lxv vs0, 0(r5)
162162
; CHECK-NEXT: lxv v3, 0(r4)
@@ -173,10 +173,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
173173
; CHECK-BE: # %bb.0: # %entry
174174
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
175175
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
176-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
176+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
177177
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
178178
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
179-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
179+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
180180
; CHECK-BE-NEXT: lxv v2, 0(r4)
181181
; CHECK-BE-NEXT: lxv vs0, 0(r5)
182182
; CHECK-BE-NEXT: lxv v3, 16(r4)
@@ -242,10 +242,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
242242
; CHECK: # %bb.0: # %entry
243243
; CHECK-NEXT: lxvp vsp34, 0(r3)
244244
; CHECK-NEXT: lxvp vsp36, 32(r3)
245-
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
245+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
246246
; CHECK-NEXT: lxvp vsp34, 64(r3)
247247
; CHECK-NEXT: lxvp vsp36, 96(r3)
248-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
248+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
249249
; CHECK-NEXT: lxv v2, 16(r4)
250250
; CHECK-NEXT: lxv vs0, 0(r5)
251251
; CHECK-NEXT: lxv v3, 0(r4)
@@ -262,10 +262,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
262262
; CHECK-BE: # %bb.0: # %entry
263263
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
264264
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
265-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
265+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
266266
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
267267
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
268-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
268+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
269269
; CHECK-BE-NEXT: lxv v2, 0(r4)
270270
; CHECK-BE-NEXT: lxv vs0, 0(r5)
271271
; CHECK-BE-NEXT: lxv v3, 16(r4)

‎llvm/test/CodeGen/PowerPC/dmr-enable.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -39,10 +39,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
3939
; CHECK: # %bb.0: # %entry
4040
; CHECK-NEXT: lxvp vsp34, 0(r3)
4141
; CHECK-NEXT: lxvp vsp36, 32(r3)
42-
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
42+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
4343
; CHECK-NEXT: lxvp vsp34, 64(r3)
4444
; CHECK-NEXT: lxvp vsp36, 96(r3)
45-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
45+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
4646
; CHECK-NEXT: dmmr dmr0, dmr0
4747
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
4848
; CHECK-NEXT: stxvp vsp34, 96(r4)
@@ -56,10 +56,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
5656
; CHECK-BE: # %bb.0: # %entry
5757
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
5858
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
59-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
59+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
6060
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
6161
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
62-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
62+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
6363
; CHECK-BE-NEXT: dmmr dmr0, dmr0
6464
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
6565
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
@@ -80,16 +80,16 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
8080
; CHECK: # %bb.0: # %entry
8181
; CHECK-NEXT: lxvp vsp34, 0(r3)
8282
; CHECK-NEXT: lxvp vsp36, 32(r3)
83-
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
83+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
8484
; CHECK-NEXT: lxvp vsp34, 64(r3)
8585
; CHECK-NEXT: lxvp vsp36, 96(r3)
86-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
86+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
8787
; CHECK-NEXT: lxvp vsp34, 0(r4)
8888
; CHECK-NEXT: lxvp vsp36, 32(r4)
89-
; CHECK-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
89+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
9090
; CHECK-NEXT: lxvp vsp34, 64(r4)
9191
; CHECK-NEXT: lxvp vsp36, 96(r4)
92-
; CHECK-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
92+
; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0
9393
; CHECK-NEXT: dmxor dmr0, dmr1
9494
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
9595
; CHECK-NEXT: stxvp vsp34, 96(r5)
@@ -103,16 +103,16 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
103103
; CHECK-BE: # %bb.0: # %entry
104104
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
105105
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
106-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
106+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
107107
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
108108
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
109-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
109+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
110110
; CHECK-BE-NEXT: lxvp vsp34, 96(r4)
111111
; CHECK-BE-NEXT: lxvp vsp36, 64(r4)
112-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
112+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
113113
; CHECK-BE-NEXT: lxvp vsp34, 32(r4)
114114
; CHECK-BE-NEXT: lxvp vsp36, 0(r4)
115-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
115+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0
116116
; CHECK-BE-NEXT: dmxor dmr0, dmr1
117117
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
118118
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)

‎llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,15 +35,15 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
3535
; CHECK-NEXT: vmr v28, v2
3636
; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
3737
; CHECK-NEXT: ld r30, 272(r1)
38-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
38+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp60, vsp62, 0
3939
; CHECK-NEXT: xvf16ger2pp wacc0, v2, v4
4040
; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
4141
; CHECK-NEXT: stxvp vsp36, 64(r1)
4242
; CHECK-NEXT: stxvp vsp34, 32(r1)
4343
; CHECK-NEXT: bl foo@notoc
4444
; CHECK-NEXT: lxvp vsp34, 64(r1)
4545
; CHECK-NEXT: lxvp vsp36, 32(r1)
46-
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
46+
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
4747
; CHECK-NEXT: xvf16ger2pp wacc0, v28, v30
4848
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
4949
; CHECK-NEXT: stxv v4, 48(r30)
@@ -82,7 +82,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
8282
; CHECK-BE-NEXT: vmr v28, v2
8383
; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill
8484
; CHECK-BE-NEXT: ld r30, 368(r1)
85-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
85+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp60, vsp62, 0
8686
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v2, v4
8787
; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
8888
; CHECK-BE-NEXT: stxvp vsp36, 112(r1)
@@ -91,7 +91,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
9191
; CHECK-BE-NEXT: nop
9292
; CHECK-BE-NEXT: lxvp vsp34, 112(r1)
9393
; CHECK-BE-NEXT: lxvp vsp36, 144(r1)
94-
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
94+
; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
9595
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v28, v30
9696
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
9797
; CHECK-BE-NEXT: stxv v5, 48(r30)

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