[RISCV] Add vector hasAndNot to enable optimizations

Author: pfusik

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -2052,14 +2052,22 @@ bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
 bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
   EVT VT = Y.getValueType();
 
-  // FIXME: Support vectors once we have tests.
   if (VT.isVector())
     return false;
 
   return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) &&
          (!isa<ConstantSDNode>(Y) || cast<ConstantSDNode>(Y)->isOpaque());
 }
 
+bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
+  EVT VT = Y.getValueType();
+
+  if (!VT.isVector())
+    return hasAndNotCompare(Y);
+
+  return Subtarget.hasStdExtZvkb();
+}
+
 bool RISCVTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
   // Zbs provides BEXT[_I], which can be used with SEQZ/SNEZ as a bit test.
   if (Subtarget.hasStdExtZbs())

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -535,6 +535,7 @@ class RISCVTargetLowering : public TargetLowering {
   bool isCheapToSpeculateCtlz(Type *Ty) const override;
   bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
   bool hasAndNotCompare(SDValue Y) const override;
+  bool hasAndNot(SDValue Y) const override;
   bool hasBitTest(SDValue X, SDValue Y) const override;
   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
       SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vandn.ll

@@ -16,9 +16,9 @@ define <8 x i8> @not_signbit_mask_v8i8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-ZVKB-LABEL: not_signbit_mask_v8i8:
 ; CHECK-ZVKB:       # %bb.0:
 ; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-ZVKB-NEXT:    vmsgt.vi v0, v8, -1
-; CHECK-ZVKB-NEXT:    vmv.v.i v8, 0
-; CHECK-ZVKB-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVKB-NEXT:    vsra.vi v8, v8, 7
+; CHECK-ZVKB-NEXT:    vnot.v v8, v8
+; CHECK-ZVKB-NEXT:    vand.vv v8, v8, v9
 ; CHECK-ZVKB-NEXT:    ret
   %cond = icmp sgt <8 x i8> %a, splat (i8 -1)
   %r = select <8 x i1> %cond, <8 x i8> %b, <8 x i8> zeroinitializer
@@ -37,9 +37,9 @@ define <4 x i16> @not_signbit_mask_v4i16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-ZVKB-LABEL: not_signbit_mask_v4i16:
 ; CHECK-ZVKB:       # %bb.0:
 ; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-ZVKB-NEXT:    vmsgt.vi v0, v8, -1
-; CHECK-ZVKB-NEXT:    vmv.v.i v8, 0
-; CHECK-ZVKB-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVKB-NEXT:    vsra.vi v8, v8, 15
+; CHECK-ZVKB-NEXT:    vnot.v v8, v8
+; CHECK-ZVKB-NEXT:    vand.vv v8, v8, v9
 ; CHECK-ZVKB-NEXT:    ret
   %cond = icmp sgt <4 x i16> %a, splat (i16 -1)
   %r = select <4 x i1> %cond, <4 x i16> %b, <4 x i16> zeroinitializer
@@ -58,9 +58,8 @@ define <2 x i32> @not_signbit_mask_v2i32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-ZVKB-LABEL: not_signbit_mask_v2i32:
 ; CHECK-ZVKB:       # %bb.0:
 ; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-ZVKB-NEXT:    vmsgt.vi v0, v8, -1
-; CHECK-ZVKB-NEXT:    vmv.v.i v8, 0
-; CHECK-ZVKB-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVKB-NEXT:    vsra.vi v8, v8, 31
+; CHECK-ZVKB-NEXT:    vandn.vv v8, v9, v8
 ; CHECK-ZVKB-NEXT:    ret
   %cond = icmp sgt <2 x i32> %a, splat (i32 -1)
   %r = select <2 x i1> %cond, <2 x i32> %b, <2 x i32> zeroinitializer
@@ -78,10 +77,10 @@ define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
 ;
 ; CHECK-ZVKB-LABEL: not_signbit_mask_v2i64:
 ; CHECK-ZVKB:       # %bb.0:
+; CHECK-ZVKB-NEXT:    li a0, 63
 ; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-ZVKB-NEXT:    vmsgt.vi v0, v8, -1
-; CHECK-ZVKB-NEXT:    vmv.v.i v8, 0
-; CHECK-ZVKB-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVKB-NEXT:    vsra.vx v8, v8, a0
+; CHECK-ZVKB-NEXT:    vandn.vv v8, v9, v8
 ; CHECK-ZVKB-NEXT:    ret
   %cond = icmp sgt <2 x i64> %a, splat (i64 -1)
   %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer

llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll

@@ -2580,9 +2580,9 @@ define <vscale x 1 x i8> @not_signbit_mask_nxv1i8(<vscale x 1 x i8> %a, <vscale
 ; CHECK-ZVKB-LABEL: not_signbit_mask_nxv1i8:
 ; CHECK-ZVKB:       # %bb.0:
 ; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-ZVKB-NEXT:    vmsgt.vi v0, v8, -1
-; CHECK-ZVKB-NEXT:    vmv.v.i v8, 0
-; CHECK-ZVKB-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVKB-NEXT:    vsra.vi v8, v8, 7
+; CHECK-ZVKB-NEXT:    vnot.v v8, v8
+; CHECK-ZVKB-NEXT:    vand.vv v8, v8, v9
 ; CHECK-ZVKB-NEXT:    ret
   %cond = icmp sgt <vscale x 1 x i8> %a, splat (i8 -1)
   %r = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %b, <vscale x 1 x i8> zeroinitializer