[MachineCombiner][NFC] Split target-dependent patterns

We split target-dependent MachineCombiner patterns into their target
folder.

This makes MachineCombiner much more target-independent.

Reviewers:
davemgreen, asavonic, rotateright, RKSimon, lukel97, LuoYuanke, topperc, mshockwave, asi-sc

Reviewed By: topperc, mshockwave

Pull Request: #87991

Author: wangpc-pp

llvm/include/llvm/CodeGen/MachineCombinerPattern.h

@@ -16,172 +16,24 @@
 
 namespace llvm {
 
+/// The combiner's goal may differ based on which pattern it is attempting
+/// to optimize.
+enum class CombinerObjective {
+  MustReduceDepth,            // The data dependency chain must be improved.
+  MustReduceRegisterPressure, // The register pressure must be reduced.
+  Default                     // The critical path must not be lengthened.
+};
+
 /// These are instruction patterns matched by the machine combiner pass.
-enum class MachineCombinerPattern {
+enum MachineCombinerPattern : unsigned {
   // These are commutative variants for reassociating a computation chain. See
   // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
   REASSOC_AX_BY,
   REASSOC_AX_YB,
   REASSOC_XA_BY,
   REASSOC_XA_YB,
 
-  // These are patterns matched by the PowerPC to reassociate FMA chains.
-  REASSOC_XY_AMM_BMM,
-  REASSOC_XMM_AMM_BMM,
-
-  // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
-  // reduce register pressure.
-  REASSOC_XY_BCA,
-  REASSOC_XY_BAC,
-
-  // These are patterns used to reduce the length of dependence chain.
-  SUBADD_OP1,
-  SUBADD_OP2,
-
-  // These are multiply-add patterns matched by the AArch64 machine combiner.
-  MULADDW_OP1,
-  MULADDW_OP2,
-  MULSUBW_OP1,
-  MULSUBW_OP2,
-  MULADDWI_OP1,
-  MULSUBWI_OP1,
-  MULADDX_OP1,
-  MULADDX_OP2,
-  MULSUBX_OP1,
-  MULSUBX_OP2,
-  MULADDXI_OP1,
-  MULSUBXI_OP1,
-  // NEON integers vectors
-  MULADDv8i8_OP1,
-  MULADDv8i8_OP2,
-  MULADDv16i8_OP1,
-  MULADDv16i8_OP2,
-  MULADDv4i16_OP1,
-  MULADDv4i16_OP2,
-  MULADDv8i16_OP1,
-  MULADDv8i16_OP2,
-  MULADDv2i32_OP1,
-  MULADDv2i32_OP2,
-  MULADDv4i32_OP1,
-  MULADDv4i32_OP2,
-
-  MULSUBv8i8_OP1,
-  MULSUBv8i8_OP2,
-  MULSUBv16i8_OP1,
-  MULSUBv16i8_OP2,
-  MULSUBv4i16_OP1,
-  MULSUBv4i16_OP2,
-  MULSUBv8i16_OP1,
-  MULSUBv8i16_OP2,
-  MULSUBv2i32_OP1,
-  MULSUBv2i32_OP2,
-  MULSUBv4i32_OP1,
-  MULSUBv4i32_OP2,
-
-  MULADDv4i16_indexed_OP1,
-  MULADDv4i16_indexed_OP2,
-  MULADDv8i16_indexed_OP1,
-  MULADDv8i16_indexed_OP2,
-  MULADDv2i32_indexed_OP1,
-  MULADDv2i32_indexed_OP2,
-  MULADDv4i32_indexed_OP1,
-  MULADDv4i32_indexed_OP2,
-
-  MULSUBv4i16_indexed_OP1,
-  MULSUBv4i16_indexed_OP2,
-  MULSUBv8i16_indexed_OP1,
-  MULSUBv8i16_indexed_OP2,
-  MULSUBv2i32_indexed_OP1,
-  MULSUBv2i32_indexed_OP2,
-  MULSUBv4i32_indexed_OP1,
-  MULSUBv4i32_indexed_OP2,
-
-  // Floating Point
-  FMULADDH_OP1,
-  FMULADDH_OP2,
-  FMULSUBH_OP1,
-  FMULSUBH_OP2,
-  FMULADDS_OP1,
-  FMULADDS_OP2,
-  FMULSUBS_OP1,
-  FMULSUBS_OP2,
-  FMULADDD_OP1,
-  FMULADDD_OP2,
-  FMULSUBD_OP1,
-  FMULSUBD_OP2,
-  FNMULSUBH_OP1,
-  FNMULSUBS_OP1,
-  FNMULSUBD_OP1,
-  FMLAv1i32_indexed_OP1,
-  FMLAv1i32_indexed_OP2,
-  FMLAv1i64_indexed_OP1,
-  FMLAv1i64_indexed_OP2,
-  FMLAv4f16_OP1,
-  FMLAv4f16_OP2,
-  FMLAv8f16_OP1,
-  FMLAv8f16_OP2,
-  FMLAv2f32_OP2,
-  FMLAv2f32_OP1,
-  FMLAv2f64_OP1,
-  FMLAv2f64_OP2,
-  FMLAv4i16_indexed_OP1,
-  FMLAv4i16_indexed_OP2,
-  FMLAv8i16_indexed_OP1,
-  FMLAv8i16_indexed_OP2,
-  FMLAv2i32_indexed_OP1,
-  FMLAv2i32_indexed_OP2,
-  FMLAv2i64_indexed_OP1,
-  FMLAv2i64_indexed_OP2,
-  FMLAv4f32_OP1,
-  FMLAv4f32_OP2,
-  FMLAv4i32_indexed_OP1,
-  FMLAv4i32_indexed_OP2,
-  FMLSv1i32_indexed_OP2,
-  FMLSv1i64_indexed_OP2,
-  FMLSv4f16_OP1,
-  FMLSv4f16_OP2,
-  FMLSv8f16_OP1,
-  FMLSv8f16_OP2,
-  FMLSv2f32_OP1,
-  FMLSv2f32_OP2,
-  FMLSv2f64_OP1,
-  FMLSv2f64_OP2,
-  FMLSv4i16_indexed_OP1,
-  FMLSv4i16_indexed_OP2,
-  FMLSv8i16_indexed_OP1,
-  FMLSv8i16_indexed_OP2,
-  FMLSv2i32_indexed_OP1,
-  FMLSv2i32_indexed_OP2,
-  FMLSv2i64_indexed_OP1,
-  FMLSv2i64_indexed_OP2,
-  FMLSv4f32_OP1,
-  FMLSv4f32_OP2,
-  FMLSv4i32_indexed_OP1,
-  FMLSv4i32_indexed_OP2,
-
-  FMULv2i32_indexed_OP1,
-  FMULv2i32_indexed_OP2,
-  FMULv2i64_indexed_OP1,
-  FMULv2i64_indexed_OP2,
-  FMULv4i16_indexed_OP1,
-  FMULv4i16_indexed_OP2,
-  FMULv4i32_indexed_OP1,
-  FMULv4i32_indexed_OP2,
-  FMULv8i16_indexed_OP1,
-  FMULv8i16_indexed_OP2,
-
-  // RISCV FMADD, FMSUB, FNMSUB patterns
-  FMADD_AX,
-  FMADD_XA,
-  FMSUB,
-  FNMSUB,
-  SHXADD_ADD_SLLI_OP1,
-  SHXADD_ADD_SLLI_OP2,
-
-  // X86 VNNI
-  DPWSSD,
-
-  FNMADD,
+  TARGET_PATTERN_START
 };
 
 } // end namespace llvm

llvm/include/llvm/CodeGen/TargetInstrInfo.h

@@ -19,6 +19,7 @@
 #include "llvm/ADT/Uniformity.h"
 #include "llvm/CodeGen/MIRFormatter.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineCombinerPattern.h"
 #include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
@@ -61,7 +62,6 @@ class TargetRegisterClass;
 class TargetRegisterInfo;
 class TargetSchedModel;
 class TargetSubtargetInfo;
-enum class MachineCombinerPattern;
 enum class MachineTraceStrategy;
 
 template <class T> class SmallVectorImpl;
@@ -1191,10 +1191,9 @@ class TargetInstrInfo : public MCInstrInfo {
   /// faster sequence.
   /// \param Root - Instruction that could be combined with one of its operands
   /// \param Patterns - Vector of possible combination patterns
-  virtual bool
-  getMachineCombinerPatterns(MachineInstr &Root,
-                             SmallVectorImpl<MachineCombinerPattern> &Patterns,
-                             bool DoRegPressureReduce) const;
+  virtual bool getMachineCombinerPatterns(MachineInstr &Root,
+                                          SmallVectorImpl<unsigned> &Patterns,
+                                          bool DoRegPressureReduce) const;
 
   /// Return true if target supports reassociation of instructions in machine
   /// combiner pass to reduce register pressure for a given BB.
@@ -1206,13 +1205,17 @@ class TargetInstrInfo : public MCInstrInfo {
 
   /// Fix up the placeholder we may add in genAlternativeCodeSequence().
   virtual void
-  finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
+  finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
                     SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
 
   /// Return true when a code sequence can improve throughput. It
   /// should be called only for instructions in loops.
   /// \param Pattern - combiner pattern
-  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
+  virtual bool isThroughputPattern(unsigned Pattern) const;
+
+  /// Return the objective of a combiner pattern.
+  /// \param Pattern - combiner pattern
+  virtual CombinerObjective getCombinerObjective(unsigned Pattern) const;
 
   /// Return true if the input \P Inst is part of a chain of dependent ops
   /// that are suitable for reassociation, otherwise return false.
@@ -1256,7 +1259,7 @@ class TargetInstrInfo : public MCInstrInfo {
   /// \param InstIdxForVirtReg - map of virtual register to instruction in
   /// InsInstr that defines it
   virtual void genAlternativeCodeSequence(
-      MachineInstr &Root, MachineCombinerPattern Pattern,
+      MachineInstr &Root, unsigned Pattern,
       SmallVectorImpl<MachineInstr *> &InsInstrs,
       SmallVectorImpl<MachineInstr *> &DelInstrs,
       DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
@@ -1270,8 +1273,7 @@ class TargetInstrInfo : public MCInstrInfo {
 
   /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
   /// reduce critical path length.
-  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
-                      MachineCombinerPattern Pattern,
+  void reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern,
                       SmallVectorImpl<MachineInstr *> &InsInstrs,
                       SmallVectorImpl<MachineInstr *> &DelInstrs,
                       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
@@ -1281,8 +1283,7 @@ class TargetInstrInfo : public MCInstrInfo {
   /// (new root opcode, new prev opcode) that must be used to reassociate \P
   /// Root and \P Prev accoring to \P Pattern.
   std::pair<unsigned, unsigned>
-  getReassociationOpcodes(MachineCombinerPattern Pattern,
-                          const MachineInstr &Root,
+  getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root,
                           const MachineInstr &Prev) const;
 
   /// The limit on resource length extension we accept in MachineCombiner Pass.