@@ -417,6 +417,30 @@ gentbl_cc_library(
417417 deps = [":RiscvTdFiles" ],
418418)
419419
420+ gentbl_cc_library (
421+ name = "basic_riscv_andes_vector_builtins_gen" ,
422+ tbl_outs = {"include/clang/Basic/riscv_andes_vector_builtins.inc" : ["-gen-riscv-andes-vector-builtins" ]},
423+ tblgen = ":clang-tblgen" ,
424+ td_file = "include/clang/Basic/riscv_andes_vector.td" ,
425+ deps = [":RiscvTdFiles" ],
426+ )
427+
428+ gentbl_cc_library (
429+ name = "basic_riscv_andes_vector_builtin_cg_gen" ,
430+ tbl_outs = {"include/clang/Basic/riscv_andes_vector_builtin_cg.inc" : ["-gen-riscv-andes-vector-builtin-codegen" ]},
431+ tblgen = ":clang-tblgen" ,
432+ td_file = "include/clang/Basic/riscv_andes_vector.td" ,
433+ deps = [":RiscvTdFiles" ],
434+ )
435+
436+ gentbl_cc_library (
437+ name = "basic_riscv_andes_vector_builtin_sema_gen" ,
438+ tbl_outs = {"include/clang/Basic/riscv_andes_vector_builtin_sema.inc" : ["-gen-riscv-andes-vector-builtin-sema" ]},
439+ tblgen = ":clang-tblgen" ,
440+ td_file = "include/clang/Basic/riscv_andes_vector.td" ,
441+ deps = [":RiscvTdFiles" ],
442+ )
443+
420444gentbl_cc_library (
421445 name = "basic_arm_cde_gen" ,
422446 tbl_outs = {"include/clang/Basic/arm_cde_builtins.inc" : ["-gen-arm-cde-builtin-def" ]},
@@ -634,6 +658,7 @@ cc_library(
634658 ":basic_builtins_spirv_gen" ,
635659 ":basic_builtins_x86_64_gen" ,
636660 ":basic_builtins_x86_gen" ,
661+ ":basic_riscv_andes_vector_builtins_gen" ,
637662 ":basic_riscv_sifive_vector_builtins_gen" ,
638663 ":basic_riscv_vector_builtin_cg_gen" ,
639664 ":basic_riscv_vector_builtins_gen" ,
@@ -993,6 +1018,7 @@ cc_library(
9931018 ":basic_arm_sve_sema_rangechecks_gen" ,
9941019 ":basic_arm_sve_streaming_attrs_gen" ,
9951020 ":basic_builtins_gen" ,
1021+ ":basic_riscv_andes_vector_builtin_sema_gen" ,
9961022 ":basic_riscv_sifive_vector_builtin_sema_gen" ,
9971023 ":basic_riscv_vector_builtin_sema_gen" ,
9981024 ":edit" ,
@@ -1725,6 +1751,7 @@ cc_library(
17251751 ":basic_arm_cde_cg_gen" ,
17261752 ":basic_arm_sme_builtin_cg_gen" ,
17271753 ":basic_arm_sve_builtin_cg_gen" ,
1754+ ":basic_riscv_andes_vector_builtin_cg_gen" ,
17281755 ":basic_riscv_sifive_vector_builtin_cg_gen" ,
17291756 ":basic_riscv_vector_builtin_cg_gen" ,
17301757 ":driver" ,
0 commit comments