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[AMDGPU] Use default check prefix in sdwa-peephole-instr-combine-sel.mir
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‎llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1,68 +1,68 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2-
# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=NOHAZARD %s
2+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=si-peephole-sdwa -o - %s | FileCheck %s
33

44
---
55
name: sdwa_opsel_hazard
66
body: |
7-
; NOHAZARD-LABEL: name: sdwa_opsel_hazard
8-
; NOHAZARD: bb.0:
9-
; NOHAZARD-NEXT: successors: %bb.7(0x40000000), %bb.8(0x40000000)
10-
; NOHAZARD-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6
11-
; NOHAZARD-NEXT: {{ $}}
12-
; NOHAZARD-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
13-
; NOHAZARD-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec_xnull = IMPLICIT_DEF
14-
; NOHAZARD-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
15-
; NOHAZARD-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[DEF1]], [[DEF2]], 0, 0, implicit $exec
16-
; NOHAZARD-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF undef [[DEF]], %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
17-
; NOHAZARD-NEXT: S_BRANCH %bb.7
18-
; NOHAZARD-NEXT: {{ $}}
19-
; NOHAZARD-NEXT: bb.1:
20-
; NOHAZARD-NEXT: successors: %bb.2(0x80000000)
21-
; NOHAZARD-NEXT: {{ $}}
22-
; NOHAZARD-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 255, implicit $exec
23-
; NOHAZARD-NEXT: [[V_AND_B32_sdwa:%[0-9]+]]:vgpr_32 = V_AND_B32_sdwa 0, undef [[GLOBAL_LOAD_DWORD_SADDR]], 0, [[V_MOV_B32_e32_]], 0, 6, 0, 5, 6, implicit $exec
24-
; NOHAZARD-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
25-
; NOHAZARD-NEXT: [[V_LSHLREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_sdwa 0, [[V_MOV_B32_e32_1]], 0, undef [[GLOBAL_LOAD_DWORD_SADDR]], 0, 6, 0, 6, 2, implicit $exec
26-
; NOHAZARD-NEXT: {{ $}}
27-
; NOHAZARD-NEXT: bb.2:
28-
; NOHAZARD-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
29-
; NOHAZARD-NEXT: {{ $}}
30-
; NOHAZARD-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF killed undef %9, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
31-
; NOHAZARD-NEXT: S_BRANCH %bb.3
32-
; NOHAZARD-NEXT: {{ $}}
33-
; NOHAZARD-NEXT: bb.3:
34-
; NOHAZARD-NEXT: successors: %bb.4(0x80000000)
35-
; NOHAZARD-NEXT: {{ $}}
36-
; NOHAZARD-NEXT: bb.4:
37-
; NOHAZARD-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
38-
; NOHAZARD-NEXT: {{ $}}
39-
; NOHAZARD-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32 = SI_IF killed undef [[SI_IF1]], %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
40-
; NOHAZARD-NEXT: S_BRANCH %bb.5
41-
; NOHAZARD-NEXT: {{ $}}
42-
; NOHAZARD-NEXT: bb.5:
43-
; NOHAZARD-NEXT: successors: %bb.6(0x80000000)
44-
; NOHAZARD-NEXT: {{ $}}
45-
; NOHAZARD-NEXT: bb.6:
46-
; NOHAZARD-NEXT: successors: %bb.9(0x40000000), %bb.10(0x40000000)
47-
; NOHAZARD-NEXT: {{ $}}
48-
; NOHAZARD-NEXT: [[SI_IF3:%[0-9]+]]:sreg_32 = SI_IF undef [[DEF]], %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
49-
; NOHAZARD-NEXT: S_BRANCH %bb.9
50-
; NOHAZARD-NEXT: {{ $}}
51-
; NOHAZARD-NEXT: bb.7:
52-
; NOHAZARD-NEXT: successors: %bb.8(0x80000000)
53-
; NOHAZARD-NEXT: {{ $}}
54-
; NOHAZARD-NEXT: bb.8:
55-
; NOHAZARD-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
56-
; NOHAZARD-NEXT: {{ $}}
57-
; NOHAZARD-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, undef [[GLOBAL_LOAD_DWORD_SADDR]], implicit $exec
58-
; NOHAZARD-NEXT: [[SI_IF4:%[0-9]+]]:sreg_32 = SI_IF killed undef [[SI_IF]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
59-
; NOHAZARD-NEXT: S_BRANCH %bb.1
60-
; NOHAZARD-NEXT: {{ $}}
61-
; NOHAZARD-NEXT: bb.9:
62-
; NOHAZARD-NEXT: successors: %bb.10(0x80000000)
63-
; NOHAZARD-NEXT: {{ $}}
64-
; NOHAZARD-NEXT: bb.10:
65-
; NOHAZARD-NEXT: S_ENDPGM 0
7+
; CHECK-LABEL: name: sdwa_opsel_hazard
8+
; CHECK: bb.0:
9+
; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.8(0x40000000)
10+
; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6
11+
; CHECK-NEXT: {{ $}}
12+
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
13+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec_xnull = IMPLICIT_DEF
14+
; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
15+
; CHECK-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[DEF1]], [[DEF2]], 0, 0, implicit $exec
16+
; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF undef [[DEF]], %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
17+
; CHECK-NEXT: S_BRANCH %bb.7
18+
; CHECK-NEXT: {{ $}}
19+
; CHECK-NEXT: bb.1:
20+
; CHECK-NEXT: successors: %bb.2(0x80000000)
21+
; CHECK-NEXT: {{ $}}
22+
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 255, implicit $exec
23+
; CHECK-NEXT: [[V_AND_B32_sdwa:%[0-9]+]]:vgpr_32 = V_AND_B32_sdwa 0, undef [[GLOBAL_LOAD_DWORD_SADDR]], 0, [[V_MOV_B32_e32_]], 0, 6, 0, 5, 6, implicit $exec
24+
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
25+
; CHECK-NEXT: [[V_LSHLREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_sdwa 0, [[V_MOV_B32_e32_1]], 0, undef [[GLOBAL_LOAD_DWORD_SADDR]], 0, 6, 0, 6, 2, implicit $exec
26+
; CHECK-NEXT: {{ $}}
27+
; CHECK-NEXT: bb.2:
28+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
29+
; CHECK-NEXT: {{ $}}
30+
; CHECK-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF killed undef %9, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
31+
; CHECK-NEXT: S_BRANCH %bb.3
32+
; CHECK-NEXT: {{ $}}
33+
; CHECK-NEXT: bb.3:
34+
; CHECK-NEXT: successors: %bb.4(0x80000000)
35+
; CHECK-NEXT: {{ $}}
36+
; CHECK-NEXT: bb.4:
37+
; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
38+
; CHECK-NEXT: {{ $}}
39+
; CHECK-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32 = SI_IF killed undef [[SI_IF1]], %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
40+
; CHECK-NEXT: S_BRANCH %bb.5
41+
; CHECK-NEXT: {{ $}}
42+
; CHECK-NEXT: bb.5:
43+
; CHECK-NEXT: successors: %bb.6(0x80000000)
44+
; CHECK-NEXT: {{ $}}
45+
; CHECK-NEXT: bb.6:
46+
; CHECK-NEXT: successors: %bb.9(0x40000000), %bb.10(0x40000000)
47+
; CHECK-NEXT: {{ $}}
48+
; CHECK-NEXT: [[SI_IF3:%[0-9]+]]:sreg_32 = SI_IF undef [[DEF]], %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
49+
; CHECK-NEXT: S_BRANCH %bb.9
50+
; CHECK-NEXT: {{ $}}
51+
; CHECK-NEXT: bb.7:
52+
; CHECK-NEXT: successors: %bb.8(0x80000000)
53+
; CHECK-NEXT: {{ $}}
54+
; CHECK-NEXT: bb.8:
55+
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
56+
; CHECK-NEXT: {{ $}}
57+
; CHECK-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, undef [[GLOBAL_LOAD_DWORD_SADDR]], implicit $exec
58+
; CHECK-NEXT: [[SI_IF4:%[0-9]+]]:sreg_32 = SI_IF killed undef [[SI_IF]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
59+
; CHECK-NEXT: S_BRANCH %bb.1
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: bb.9:
62+
; CHECK-NEXT: successors: %bb.10(0x80000000)
63+
; CHECK-NEXT: {{ $}}
64+
; CHECK-NEXT: bb.10:
65+
; CHECK-NEXT: S_ENDPGM 0
6666
bb.0:
6767
successors: %bb.7(0x40000000), %bb.8(0x40000000)
6868
liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6

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