implement feedback

Author: ro-i

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -482,10 +482,10 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
       return (LA & LB).any();
     }
     if (RegA.isPhysical() && RegB.isPhysical()) {
-      RegA = getSubReg(RegA.asMCReg(), SubA);
-      RegB = getSubReg(RegB.asMCReg(), SubB);
-      assert(RegB.isValid() && RegA.isValid() && "invalid subregister");
-      return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
+      MCRegister MCRegA = SubA ? getSubReg(RegA, SubA) : RegA.asMCReg();
+      MCRegister MCRegB = SubB ? getSubReg(RegB, SubB) : RegB.asMCReg();
+      assert(MCRegB.isValid() && MCRegA.isValid() && "invalid subregister");
+      return MCRegisterInfo::regsOverlap(MCRegA, MCRegB);
     }
     return false;
   }

llvm/lib/MC/MCRegisterInfo.cpp

@@ -114,9 +114,8 @@ MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
 }
 
 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {
-  if (!Idx)
-    return Reg;
-  assert(Idx < getNumSubRegIndices() && "This is not a subregister index");
+  assert(Idx && Idx < getNumSubRegIndices() &&
+         "This is not a subregister index");
   // Get a pointer to the corresponding SubRegIndices list. This list has the
   // name of each sub-register in the same order as MCSubRegIterator.
   const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;

llvm/lib/Target/AMDGPU/GCNSubtarget.cpp

@@ -657,7 +657,7 @@ getVOP3PSourceModifierFromOpIdx(const MachineInstr *UseI, int UseOpIdx,
 // Get the subreg idx of the subreg that is used by the given instruction
 // operand, considering the given op_sel modifier.
 // Return 0 if the whole register is used or as a conservative fallback.
-static unsigned getEffectiveSubRegIdx(const SIRegisterInfo *TRI,
+static unsigned getEffectiveSubRegIdx(const SIRegisterInfo &TRI,
                                       const SIInstrInfo &InstrInfo,
                                       const MachineOperand &Op) {
   const MachineInstr *I = Op.getParent();
@@ -691,14 +691,14 @@ static unsigned getEffectiveSubRegIdx(const SIRegisterInfo *TRI,
       (InstrInfo.isVOP3PMix(*I) && !OpSelHi))
     return 0;
 
-  const TargetRegisterClass *RC =
-      InstrInfo.getOpRegClass(*I, Op.getOperandNo());
+  const MachineRegisterInfo &MRI = I->getParent()->getParent()->getRegInfo();
+  const TargetRegisterClass *RC = TRI.getRegClassForOperandReg(MRI, Op);
 
   if (unsigned SubRegIdx = OpSel ? AMDGPU::sub1 : AMDGPU::sub0;
-      TRI->getSubRegisterClass(RC, SubRegIdx))
+      TRI.getSubClassWithSubReg(RC, SubRegIdx) == RC)
     return SubRegIdx;
   if (unsigned SubRegIdx = OpSel ? AMDGPU::hi16 : AMDGPU::lo16;
-      TRI->getSubRegisterClass(RC, SubRegIdx))
+      TRI.getSubClassWithSubReg(RC, SubRegIdx) == RC)
     return SubRegIdx;
 
   return 0;
@@ -722,7 +722,7 @@ Register GCNSubtarget::getRealSchedDependency(const MachineInstr *DefI,
   unsigned DefSubRegIdx = DefOp.getSubReg();
   if (DefReg.isVirtual() && !DefSubRegIdx)
     return DefReg;
-  unsigned UseSubRegIdx = getEffectiveSubRegIdx(TRI, InstrInfo, UseOp);
+  unsigned UseSubRegIdx = getEffectiveSubRegIdx(*TRI, InstrInfo, UseOp);
   if (UseReg.isVirtual() && !UseSubRegIdx)
     return DefReg;
 
@@ -734,8 +734,10 @@ Register GCNSubtarget::getRealSchedDependency(const MachineInstr *DefI,
   // apply to virtual registers because we cannot construct a subreg for them.
   if (DefReg.isVirtual())
     return DefReg;
-  MCRegister DefMCReg = TRI->getSubReg(DefReg.asMCReg(), DefSubRegIdx);
-  MCRegister UseMCReg = TRI->getSubReg(UseReg.asMCReg(), UseSubRegIdx);
+  MCRegister DefMCReg =
+      DefSubRegIdx ? TRI->getSubReg(DefReg, DefSubRegIdx) : DefReg.asMCReg();
+  MCRegister UseMCReg =
+      UseSubRegIdx ? TRI->getSubReg(UseReg, UseSubRegIdx) : UseReg.asMCReg();
   const TargetRegisterClass *DefRC = TRI->getPhysRegBaseClass(DefMCReg);
   const TargetRegisterClass *UseRC = TRI->getPhysRegBaseClass(UseMCReg);
   // Some registers, such as SGPR[0-9]+_HI16, do not have a register class.