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Move to new test without FileCheck/UTC
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‎llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl -prefer-predicate-over-epilogue=predicate-dont-vectorize -mtriple=riscv64 -mattr=+v -S %s
2+
3+
; Make sure we don't crash when transforming a VPWidenCastRecipe is created
4+
; without an underlying value. This occurs in this test via
5+
; VPlanTransforms::truncateToMinimalBitwidths
6+
7+
define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %dst, ptr %src, i32 %mvx) {
8+
entry:
9+
%cmp111 = icmp sgt i32 %mvx, 0
10+
br i1 %cmp111, label %for.body13.preheader, label %for.cond.cleanup12
11+
12+
for.body13.preheader: ; preds = %entry
13+
%wide.trip.count = zext nneg i32 %mvx to i64
14+
br label %for.body13
15+
16+
for.body13: ; preds = %for.body13.preheader, %for.body13
17+
%indvars.iv = phi i64 [ 0, %for.body13.preheader ], [ %indvars.iv.next, %for.body13 ]
18+
%arrayidx15 = getelementptr i8, ptr %src, i64 %indvars.iv
19+
%0 = load i8, ptr %arrayidx15, align 1
20+
%conv = zext i8 %0 to i32
21+
%mul16 = mul i32 %mvx, %conv
22+
%shr35 = lshr i32 %mul16, 1
23+
%conv36 = trunc i32 %shr35 to i8
24+
store i8 %conv36, ptr %dst, align 1
25+
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
26+
%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
27+
br i1 %exitcond.not, label %for.cond.cleanup12, label %for.body13
28+
29+
for.cond.cleanup12: ; preds = %for.body13, %entry
30+
ret void
31+
}

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll‎

Lines changed: 0 additions & 118 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,122 +1058,6 @@ loop:
10581058
exit:
10591059
ret void
10601060
}
1061-
1062-
define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr noalias %dst, ptr noalias %src, i32 %mvx) {
1063-
; IF-EVL-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe(
1064-
; IF-EVL-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i32 [[MVX:%.*]]) #[[ATTR0]] {
1065-
; IF-EVL-NEXT: [[ENTRY:.*:]]
1066-
; IF-EVL-NEXT: [[CMP111:%.*]] = icmp sgt i32 [[MVX]], 0
1067-
; IF-EVL-NEXT: br i1 [[CMP111]], label %[[FOR_BODY13_PREHEADER:.*]], label %[[FOR_COND_CLEANUP12:.*]]
1068-
; IF-EVL: [[FOR_BODY13_PREHEADER]]:
1069-
; IF-EVL-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[MVX]] to i64
1070-
; IF-EVL-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
1071-
; IF-EVL: [[VECTOR_PH]]:
1072-
; IF-EVL-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
1073-
; IF-EVL-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 16
1074-
; IF-EVL-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], 1
1075-
; IF-EVL-NEXT: [[N_RND_UP:%.*]] = add i64 [[WIDE_TRIP_COUNT]], [[TMP2]]
1076-
; IF-EVL-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP1]]
1077-
; IF-EVL-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
1078-
; IF-EVL-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
1079-
; IF-EVL-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 16
1080-
; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x i32> poison, i32 [[MVX]], i64 0
1081-
; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
1082-
; IF-EVL-NEXT: [[TMP5:%.*]] = trunc <vscale x 16 x i32> [[BROADCAST_SPLAT]] to <vscale x 16 x i16>
1083-
; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <vscale x 16 x ptr> poison, ptr [[DST]], i64 0
1084-
; IF-EVL-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <vscale x 16 x ptr> [[BROADCAST_SPLATINSERT2]], <vscale x 16 x ptr> poison, <vscale x 16 x i32> zeroinitializer
1085-
; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]
1086-
; IF-EVL: [[VECTOR_BODY]]:
1087-
; IF-EVL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
1088-
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
1089-
; IF-EVL-NEXT: [[AVL:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[EVL_BASED_IV]]
1090-
; IF-EVL-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 16, i1 true)
1091-
; IF-EVL-NEXT: [[TMP7:%.*]] = add i64 [[EVL_BASED_IV]], 0
1092-
; IF-EVL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP7]]
1093-
; IF-EVL-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP8]], i32 0
1094-
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 16 x i8> @llvm.vp.load.nxv16i8.p0(ptr align 1 [[TMP9]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
1095-
; IF-EVL-NEXT: [[TMP10:%.*]] = call <vscale x 16 x i16> @llvm.vp.zext.nxv16i16.nxv16i8(<vscale x 16 x i8> [[VP_OP_LOAD]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
1096-
; IF-EVL-NEXT: [[VP_OP:%.*]] = call <vscale x 16 x i16> @llvm.vp.mul.nxv16i16(<vscale x 16 x i16> [[TMP5]], <vscale x 16 x i16> [[TMP10]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
1097-
; IF-EVL-NEXT: [[VP_OP1:%.*]] = call <vscale x 16 x i16> @llvm.vp.lshr.nxv16i16(<vscale x 16 x i16> [[VP_OP]], <vscale x 16 x i16> trunc (<vscale x 16 x i32> splat (i32 1) to <vscale x 16 x i16>), <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
1098-
; IF-EVL-NEXT: [[TMP11:%.*]] = call <vscale x 16 x i8> @llvm.vp.trunc.nxv16i8.nxv16i16(<vscale x 16 x i16> [[VP_OP1]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
1099-
; IF-EVL-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> [[TMP11]], <vscale x 16 x ptr> align 1 [[BROADCAST_SPLAT3]], <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]])
1100-
; IF-EVL-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64
1101-
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP12]], [[EVL_BASED_IV]]
1102-
; IF-EVL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP4]]
1103-
; IF-EVL-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
1104-
; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP47:![0-9]+]]
1105-
; IF-EVL: [[MIDDLE_BLOCK]]:
1106-
; IF-EVL-NEXT: br i1 true, label %[[FOR_COND_CLEANUP12_LOOPEXIT:.*]], label %[[SCALAR_PH]]
1107-
; IF-EVL: [[SCALAR_PH]]:
1108-
; IF-EVL-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY13_PREHEADER]] ]
1109-
; IF-EVL-NEXT: br label %[[FOR_BODY13:.*]]
1110-
; IF-EVL: [[FOR_BODY13]]:
1111-
; IF-EVL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ]
1112-
; IF-EVL-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]]
1113-
; IF-EVL-NEXT: [[TMP14:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1
1114-
; IF-EVL-NEXT: [[CONV:%.*]] = zext i8 [[TMP14]] to i32
1115-
; IF-EVL-NEXT: [[MUL16:%.*]] = mul i32 [[MVX]], [[CONV]]
1116-
; IF-EVL-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1
1117-
; IF-EVL-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8
1118-
; IF-EVL-NEXT: store i8 [[CONV36]], ptr [[DST]], align 1
1119-
; IF-EVL-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
1120-
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
1121-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT]], label %[[FOR_BODY13]], !llvm.loop [[LOOP48:![0-9]+]]
1122-
; IF-EVL: [[FOR_COND_CLEANUP12_LOOPEXIT]]:
1123-
; IF-EVL-NEXT: br label %[[FOR_COND_CLEANUP12]]
1124-
; IF-EVL: [[FOR_COND_CLEANUP12]]:
1125-
; IF-EVL-NEXT: ret void
1126-
;
1127-
; NO-VP-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe(
1128-
; NO-VP-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i32 [[MVX:%.*]]) #[[ATTR0]] {
1129-
; NO-VP-NEXT: [[ENTRY:.*:]]
1130-
; NO-VP-NEXT: [[CMP111:%.*]] = icmp sgt i32 [[MVX]], 0
1131-
; NO-VP-NEXT: br i1 [[CMP111]], label %[[FOR_BODY13_PREHEADER:.*]], label %[[FOR_COND_CLEANUP12:.*]]
1132-
; NO-VP: [[FOR_BODY13_PREHEADER]]:
1133-
; NO-VP-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[MVX]] to i64
1134-
; NO-VP-NEXT: br label %[[FOR_BODY13:.*]]
1135-
; NO-VP: [[FOR_BODY13]]:
1136-
; NO-VP-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_BODY13_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ]
1137-
; NO-VP-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]]
1138-
; NO-VP-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1
1139-
; NO-VP-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
1140-
; NO-VP-NEXT: [[MUL16:%.*]] = mul i32 [[MVX]], [[CONV]]
1141-
; NO-VP-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1
1142-
; NO-VP-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8
1143-
; NO-VP-NEXT: store i8 [[CONV36]], ptr [[DST]], align 1
1144-
; NO-VP-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
1145-
; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
1146-
; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT:.*]], label %[[FOR_BODY13]]
1147-
; NO-VP: [[FOR_COND_CLEANUP12_LOOPEXIT]]:
1148-
; NO-VP-NEXT: br label %[[FOR_COND_CLEANUP12]]
1149-
; NO-VP: [[FOR_COND_CLEANUP12]]:
1150-
; NO-VP-NEXT: ret void
1151-
;
1152-
entry:
1153-
%cmp111 = icmp sgt i32 %mvx, 0
1154-
br i1 %cmp111, label %for.body13.preheader, label %for.cond.cleanup12
1155-
1156-
for.body13.preheader: ; preds = %entry
1157-
%wide.trip.count = zext nneg i32 %mvx to i64
1158-
br label %for.body13
1159-
1160-
for.body13: ; preds = %for.body13.preheader, %for.body13
1161-
%indvars.iv = phi i64 [ 0, %for.body13.preheader ], [ %indvars.iv.next, %for.body13 ]
1162-
%arrayidx15 = getelementptr i8, ptr %src, i64 %indvars.iv
1163-
%0 = load i8, ptr %arrayidx15, align 1
1164-
%conv = zext i8 %0 to i32
1165-
%mul16 = mul i32 %mvx, %conv
1166-
%shr35 = lshr i32 %mul16, 1
1167-
%conv36 = trunc i32 %shr35 to i8
1168-
store i8 %conv36, ptr %dst, align 1
1169-
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
1170-
%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
1171-
br i1 %exitcond.not, label %for.cond.cleanup12, label %for.body13
1172-
1173-
for.cond.cleanup12: ; preds = %for.body13, %entry
1174-
ret void
1175-
}
1176-
11771061
;.
11781062
; IF-EVL: [[META0]] = !{[[META1:![0-9]+]]}
11791063
; IF-EVL: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}
@@ -1222,6 +1106,4 @@ for.cond.cleanup12: ; preds = %for.body13, %entry
12221106
; IF-EVL: [[LOOP44]] = distinct !{[[LOOP44]], [[META6]]}
12231107
; IF-EVL: [[LOOP45]] = distinct !{[[LOOP45]], [[META6]], [[META7]]}
12241108
; IF-EVL: [[LOOP46]] = distinct !{[[LOOP46]], [[META6]]}
1225-
; IF-EVL: [[LOOP47]] = distinct !{[[LOOP47]], [[META6]], [[META7]]}
1226-
; IF-EVL: [[LOOP48]] = distinct !{[[LOOP48]], [[META7]], [[META6]]}
12271109
;.

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