@@ -90,6 +90,25 @@ static mlir::Value getMaskVecValue(CIRGenFunction &cgf, const CallExpr *expr,
9090 return maskVec;
9191}
9292
93+ static mlir::Value emitX86FunnelShift (CIRGenFunction &cgf, const CallExpr *e,
94+ mlir::Value &op0, mlir::Value &op1,
95+ mlir::Value &amt, bool isRight) {
96+ auto ty = op0.getType ();
97+
98+ // Amount may be scalar immediate, in which case create a splat vector.
99+ // Funnel shifts amounts are treated as modulo and types are all power-of-2
100+ // so we only care about the lowest log2 bits anyway.
101+ if (amt.getType () != ty) {
102+ amt = cgf.getBuilder ().createIntCast (
103+ amt, mlir::cast<cir::VectorType>(ty).getElementType ());
104+ amt = cir::VecSplatOp::create (cgf.getBuilder (), cgf.getLoc (e->getExprLoc ()),
105+ ty, amt);
106+ }
107+
108+ const std::string intrinsicName = isRight ? " fshr" : " fshl" ;
109+ return emitIntrinsicCallOp (cgf, e, intrinsicName, ty, op0, op1, amt);
110+ }
111+
93112mlir::Value CIRGenFunction::emitX86BuiltinExpr (unsigned builtinID,
94113 const CallExpr *expr) {
95114 if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -109,14 +128,15 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
109128 // evaluation.
110129 assert (!cir::MissingFeatures::msvcBuiltins ());
111130
112- // Find out if any arguments are required to be integer constant expressions.
131+ // Find out if any arguments are required to be integer constant
132+ // expressions.
113133 assert (!cir::MissingFeatures::handleBuiltinICEArguments ());
114134
115135 // The operands of the builtin call
116136 llvm::SmallVector<mlir::Value> ops;
117137
118- // `ICEArguments` is a bitmap indicating whether the argument at the i-th bit
119- // is required to be a constant integer expression.
138+ // `ICEArguments` is a bitmap indicating whether the argument at the i-th
139+ // bit is required to be a constant integer expression.
120140 unsigned iceArguments = 0 ;
121141 ASTContext::GetBuiltinTypeError error;
122142 getContext ().GetBuiltinType (builtinID, error, &iceArguments);
@@ -661,12 +681,14 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
661681 case X86::BI__builtin_ia32_prolq128:
662682 case X86::BI__builtin_ia32_prolq256:
663683 case X86::BI__builtin_ia32_prolq512:
684+ return emitX86FunnelShift (*this , e, ops[0 ], ops[1 ], ops[1 ], false );
664685 case X86::BI__builtin_ia32_prord128:
665686 case X86::BI__builtin_ia32_prord256:
666687 case X86::BI__builtin_ia32_prord512:
667688 case X86::BI__builtin_ia32_prorq128:
668689 case X86::BI__builtin_ia32_prorq256:
669690 case X86::BI__builtin_ia32_prorq512:
691+ return emitX86FunnelShift (*this , e, ops[0 ], ops[1 ], ops[1 ], true );
670692 case X86::BI__builtin_ia32_selectb_128:
671693 case X86::BI__builtin_ia32_selectb_256:
672694 case X86::BI__builtin_ia32_selectb_512:
0 commit comments