@@ -11529,12 +11529,12 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
1152911529 return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
1153011530
1153111531 unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
11532- if (TLI.isOperationLegal (IEEEOpcode, VT))
11532+ if (TLI.isOperationLegalOrCustom (IEEEOpcode, VT))
1153311533 return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
1153411534
1153511535 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
1153611536 if (TLI.isOperationLegal(Opcode, TransformVT))
11537- return DAG.getNode (Opcode, DL, VT, LHS, RHS);
11537+ return DAG.getNodeOrCustom (Opcode, DL, VT, LHS, RHS);
1153811538 return SDValue();
1153911539 }
1154011540 case ISD::SETOGT:
@@ -11553,11 +11553,11 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
1155311553 return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
1155411554
1155511555 unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
11556- if (TLI.isOperationLegal (IEEEOpcode, VT))
11556+ if (TLI.isOperationLegalOrCustom (IEEEOpcode, VT))
1155711557 return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
1155811558
1155911559 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
11560- if (TLI.isOperationLegal (Opcode, TransformVT))
11560+ if (TLI.isOperationLegalOrCustom (Opcode, TransformVT))
1156111561 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
1156211562 return SDValue();
1156311563 }
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