[llvm-exegesis] Simplifying the FPR8 setReg implementation and corresponding test cases.

Author: lakshayk-nv

llvm/test/tools/llvm-exegesis/AArch64/setReg_init_check.s

@@ -60,8 +60,7 @@ RUN: llvm-exegesis -mcpu=neoverse-v2 -mode=latency --dump-object-to-disk=%d --op
 RUN: llvm-objdump -d %d > %t.s
 RUN: FileCheck %s --check-prefix=FPR8-ASM < %t.s
 FPR8-ASM:         <foo>:
-FPR8-ASM:         mov     w{{[0-9]+}}, #0x0
-FPR8-ASM-NEXT:    fmov    h{{[0-9]+}}, w{{[0-9]+}}
+FPR8-ASM:         movi d{{[0-9]+}}, #0000000000000000
 FPR8-ASM-NEXT:    sqabs   b{{[0-9]+}}, b{{[0-9]+}}
 
 
@@ -71,6 +70,6 @@ RUN: llvm-objdump -d %d > %t.s
 RUN: FileCheck %s --check-prefix=FPCR-ASM < %t.s
 FPCR-ASM:         <foo>:
 FPCR-ASM:         movi d{{[0-9]+}}, #0000000000000000
-FPCR-ASM-NEXT:    mov     x{{[0-9]+}}, #0x0
-FPCR-ASM-NEXT:    msr     FPCR, x{{[0-9]+}}
+FPCR-ASM-NEXT:    mov     x8, #0x0
+FPCR-ASM-NEXT:    msr     FPCR, x8
 FPCR-ASM-NEXT:    bfcvt   h{{[0-9]+}}, s{{[0-9]+}}

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

@@ -63,27 +63,6 @@ loadFPCRImmediate(MCRegister Reg, unsigned RegBitWidth, const APInt &Value) {
   return {LoadImm, MoveToFPCR};
 }
 
-// Generates instructions to load an immediate value into an FPR8 register.
-static std::vector<MCInst>
-loadFP8Immediate(MCRegister Reg, unsigned RegBitWidth, const APInt &Value) {
-  assert(Value.getBitWidth() <= 8 && "Value must fit in 8 bits");
-
-  // Use a temporary general-purpose register (W8) to hold the 8-bit value
-  MCRegister TempReg = AArch64::W8;
-
-  // Load the 8-bit value into a general-purpose register (W8)
-  MCInst LoadImm = MCInstBuilder(AArch64::MOVi32imm)
-                       .addReg(TempReg)
-                       .addImm(Value.getZExtValue());
-
-  // Move the value from the general-purpose register to the FPR16 register
-  // Convert the FPR8 register to an FPR16 register
-  MCRegister FPR16Reg = Reg + (AArch64::H0 - AArch64::B0);
-  MCInst MoveToFPR =
-      MCInstBuilder(AArch64::FMOVWHr).addReg(FPR16Reg).addReg(TempReg);
-  return {LoadImm, MoveToFPR};
-}
-
 // Fetch base-instruction to load an FP immediate value into a register.
 static unsigned getLoadFPImmediateOpcode(unsigned RegBitWidth) {
   switch (RegBitWidth) {
@@ -129,7 +108,7 @@ class ExegesisAArch64Target : public ExegesisTarget {
     if (AArch64::PPRRegClass.contains(Reg))
       return {loadPPRImmediate(Reg, 16, Value)};
     if (AArch64::FPR8RegClass.contains(Reg))
-      return loadFP8Immediate(Reg, 8, Value);
+      return {loadFPImmediate(Reg - AArch64::B0 + AArch64::D0, 64, Value)};
     if (AArch64::FPR16RegClass.contains(Reg))
       return {loadFPImmediate(Reg, 16, Value)};
     if (AArch64::FPR32RegClass.contains(Reg))