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‎llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -3011,8 +3011,8 @@ entry:
30113011
ret <4 x double> %log2
30123012
}
30133013

3014-
define <1 x float> @constrained_vector_rint_v1f32(ptr %a) #0 {
3015-
; CHECK-LABEL: constrained_vector_rint_v1f32:
3014+
define <1 x float> @constrained_vector_rint_v1f32_var(ptr %a) #0 {
3015+
; CHECK-LABEL: constrained_vector_rint_v1f32_var:
30163016
; CHECK: # %bb.0: # %entry
30173017
; CHECK-NEXT: pushq %rax
30183018
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -3022,7 +3022,7 @@ define <1 x float> @constrained_vector_rint_v1f32(ptr %a) #0 {
30223022
; CHECK-NEXT: .cfi_def_cfa_offset 8
30233023
; CHECK-NEXT: retq
30243024
;
3025-
; AVX-LABEL: constrained_vector_rint_v1f32:
3025+
; AVX-LABEL: constrained_vector_rint_v1f32_var:
30263026
; AVX: # %bb.0: # %entry
30273027
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
30283028
; AVX-NEXT: vroundss $4, %xmm0, %xmm0, %xmm0
@@ -3096,8 +3096,8 @@ entry:
30963096
ret <2 x double> %rint
30973097
}
30983098

3099-
define <3 x float> @constrained_vector_rint_v3f32(ptr %a) #0 {
3100-
; CHECK-LABEL: constrained_vector_rint_v3f32:
3099+
define <3 x float> @constrained_vector_rint_v3f32_var(ptr %a) #0 {
3100+
; CHECK-LABEL: constrained_vector_rint_v3f32_var:
31013101
; CHECK: # %bb.0: # %entry
31023102
; CHECK-NEXT: subq $56, %rsp
31033103
; CHECK-NEXT: .cfi_def_cfa_offset 64
@@ -3120,7 +3120,7 @@ define <3 x float> @constrained_vector_rint_v3f32(ptr %a) #0 {
31203120
; CHECK-NEXT: .cfi_def_cfa_offset 8
31213121
; CHECK-NEXT: retq
31223122
;
3123-
; AVX-LABEL: constrained_vector_rint_v3f32:
3123+
; AVX-LABEL: constrained_vector_rint_v3f32_var:
31243124
; AVX: # %bb.0: # %entry
31253125
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
31263126
; AVX-NEXT: vroundss $4, %xmm0, %xmm0, %xmm0
@@ -3307,8 +3307,8 @@ entry:
33073307
ret <4 x double> %rint
33083308
}
33093309

3310-
define <1 x float> @constrained_vector_nearbyint_v1f32(ptr %a) #0 {
3311-
; CHECK-LABEL: constrained_vector_nearbyint_v1f32:
3310+
define <1 x float> @constrained_vector_nearbyint_v1f32_var(ptr %a) #0 {
3311+
; CHECK-LABEL: constrained_vector_nearbyint_v1f32_var:
33123312
; CHECK: # %bb.0: # %entry
33133313
; CHECK-NEXT: pushq %rax
33143314
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -3318,7 +3318,7 @@ define <1 x float> @constrained_vector_nearbyint_v1f32(ptr %a) #0 {
33183318
; CHECK-NEXT: .cfi_def_cfa_offset 8
33193319
; CHECK-NEXT: retq
33203320
;
3321-
; AVX-LABEL: constrained_vector_nearbyint_v1f32:
3321+
; AVX-LABEL: constrained_vector_nearbyint_v1f32_var:
33223322
; AVX: # %bb.0: # %entry
33233323
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
33243324
; AVX-NEXT: vroundss $12, %xmm0, %xmm0, %xmm0
@@ -3392,8 +3392,8 @@ entry:
33923392
ret <2 x double> %nearby
33933393
}
33943394

3395-
define <3 x float> @constrained_vector_nearbyint_v3f32(ptr %a) #0 {
3396-
; CHECK-LABEL: constrained_vector_nearbyint_v3f32:
3395+
define <3 x float> @constrained_vector_nearbyint_v3f32_var(ptr %a) #0 {
3396+
; CHECK-LABEL: constrained_vector_nearbyint_v3f32_var:
33973397
; CHECK: # %bb.0: # %entry
33983398
; CHECK-NEXT: subq $56, %rsp
33993399
; CHECK-NEXT: .cfi_def_cfa_offset 64
@@ -3416,7 +3416,7 @@ define <3 x float> @constrained_vector_nearbyint_v3f32(ptr %a) #0 {
34163416
; CHECK-NEXT: .cfi_def_cfa_offset 8
34173417
; CHECK-NEXT: retq
34183418
;
3419-
; AVX-LABEL: constrained_vector_nearbyint_v3f32:
3419+
; AVX-LABEL: constrained_vector_nearbyint_v3f32_var:
34203420
; AVX: # %bb.0: # %entry
34213421
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
34223422
; AVX-NEXT: vroundss $12, %xmm0, %xmm0, %xmm0
@@ -5870,8 +5870,8 @@ entry:
58705870
ret <4 x double> %result
58715871
}
58725872

5873-
define <1 x float> @constrained_vector_ceil_v1f32(ptr %a) #0 {
5874-
; CHECK-LABEL: constrained_vector_ceil_v1f32:
5873+
define <1 x float> @constrained_vector_ceil_v1f32_var(ptr %a) #0 {
5874+
; CHECK-LABEL: constrained_vector_ceil_v1f32_var:
58755875
; CHECK: # %bb.0: # %entry
58765876
; CHECK-NEXT: pushq %rax
58775877
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -5881,7 +5881,7 @@ define <1 x float> @constrained_vector_ceil_v1f32(ptr %a) #0 {
58815881
; CHECK-NEXT: .cfi_def_cfa_offset 8
58825882
; CHECK-NEXT: retq
58835883
;
5884-
; AVX-LABEL: constrained_vector_ceil_v1f32:
5884+
; AVX-LABEL: constrained_vector_ceil_v1f32_var:
58855885
; AVX: # %bb.0: # %entry
58865886
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
58875887
; AVX-NEXT: vroundss $10, %xmm0, %xmm0, %xmm0
@@ -5894,8 +5894,8 @@ entry:
58945894
ret <1 x float> %ceil
58955895
}
58965896

5897-
define <2 x double> @constrained_vector_ceil_v2f64(ptr %a) #0 {
5898-
; CHECK-LABEL: constrained_vector_ceil_v2f64:
5897+
define <2 x double> @constrained_vector_ceil_v2f64_var(ptr %a) #0 {
5898+
; CHECK-LABEL: constrained_vector_ceil_v2f64_var:
58995899
; CHECK: # %bb.0: # %entry
59005900
; CHECK-NEXT: subq $40, %rsp
59015901
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -5913,7 +5913,7 @@ define <2 x double> @constrained_vector_ceil_v2f64(ptr %a) #0 {
59135913
; CHECK-NEXT: .cfi_def_cfa_offset 8
59145914
; CHECK-NEXT: retq
59155915
;
5916-
; AVX-LABEL: constrained_vector_ceil_v2f64:
5916+
; AVX-LABEL: constrained_vector_ceil_v2f64_var:
59175917
; AVX: # %bb.0: # %entry
59185918
; AVX-NEXT: vroundpd $10, (%rdi), %xmm0
59195919
; AVX-NEXT: retq
@@ -5925,8 +5925,8 @@ entry:
59255925
ret <2 x double> %ceil
59265926
}
59275927

5928-
define <3 x float> @constrained_vector_ceil_v3f32(ptr %a) #0 {
5929-
; CHECK-LABEL: constrained_vector_ceil_v3f32:
5928+
define <3 x float> @constrained_vector_ceil_v3f32_var(ptr %a) #0 {
5929+
; CHECK-LABEL: constrained_vector_ceil_v3f32_var:
59305930
; CHECK: # %bb.0: # %entry
59315931
; CHECK-NEXT: subq $56, %rsp
59325932
; CHECK-NEXT: .cfi_def_cfa_offset 64
@@ -5949,7 +5949,7 @@ define <3 x float> @constrained_vector_ceil_v3f32(ptr %a) #0 {
59495949
; CHECK-NEXT: .cfi_def_cfa_offset 8
59505950
; CHECK-NEXT: retq
59515951
;
5952-
; AVX-LABEL: constrained_vector_ceil_v3f32:
5952+
; AVX-LABEL: constrained_vector_ceil_v3f32_var:
59535953
; AVX: # %bb.0: # %entry
59545954
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
59555955
; AVX-NEXT: vroundss $10, %xmm0, %xmm0, %xmm0
@@ -5968,8 +5968,8 @@ entry:
59685968
ret <3 x float> %ceil
59695969
}
59705970

5971-
define <3 x double> @constrained_vector_ceil_v3f64(ptr %a) #0 {
5972-
; CHECK-LABEL: constrained_vector_ceil_v3f64:
5971+
define <3 x double> @constrained_vector_ceil_v3f64_var(ptr %a) #0 {
5972+
; CHECK-LABEL: constrained_vector_ceil_v3f64_var:
59735973
; CHECK: # %bb.0: # %entry
59745974
; CHECK-NEXT: subq $40, %rsp
59755975
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -5997,7 +5997,7 @@ define <3 x double> @constrained_vector_ceil_v3f64(ptr %a) #0 {
59975997
; CHECK-NEXT: .cfi_def_cfa_offset 8
59985998
; CHECK-NEXT: retq
59995999
;
6000-
; AVX-LABEL: constrained_vector_ceil_v3f64:
6000+
; AVX-LABEL: constrained_vector_ceil_v3f64_var:
60016001
; AVX: # %bb.0: # %entry
60026002
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
60036003
; AVX-NEXT: vroundsd $10, %xmm0, %xmm0, %xmm0
@@ -6012,8 +6012,8 @@ entry:
60126012
ret <3 x double> %ceil
60136013
}
60146014

6015-
define <1 x float> @constrained_vector_floor_v1f32(ptr %a) #0 {
6016-
; CHECK-LABEL: constrained_vector_floor_v1f32:
6015+
define <1 x float> @constrained_vector_floor_v1f32_var(ptr %a) #0 {
6016+
; CHECK-LABEL: constrained_vector_floor_v1f32_var:
60176017
; CHECK: # %bb.0: # %entry
60186018
; CHECK-NEXT: pushq %rax
60196019
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -6023,7 +6023,7 @@ define <1 x float> @constrained_vector_floor_v1f32(ptr %a) #0 {
60236023
; CHECK-NEXT: .cfi_def_cfa_offset 8
60246024
; CHECK-NEXT: retq
60256025
;
6026-
; AVX-LABEL: constrained_vector_floor_v1f32:
6026+
; AVX-LABEL: constrained_vector_floor_v1f32_var:
60276027
; AVX: # %bb.0: # %entry
60286028
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
60296029
; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm0
@@ -6037,8 +6037,8 @@ entry:
60376037
}
60386038

60396039

6040-
define <2 x double> @constrained_vector_floor_v2f64(ptr %a) #0 {
6041-
; CHECK-LABEL: constrained_vector_floor_v2f64:
6040+
define <2 x double> @constrained_vector_floor_v2f64_var(ptr %a) #0 {
6041+
; CHECK-LABEL: constrained_vector_floor_v2f64_var:
60426042
; CHECK: # %bb.0: # %entry
60436043
; CHECK-NEXT: subq $40, %rsp
60446044
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -6056,7 +6056,7 @@ define <2 x double> @constrained_vector_floor_v2f64(ptr %a) #0 {
60566056
; CHECK-NEXT: .cfi_def_cfa_offset 8
60576057
; CHECK-NEXT: retq
60586058
;
6059-
; AVX-LABEL: constrained_vector_floor_v2f64:
6059+
; AVX-LABEL: constrained_vector_floor_v2f64_var:
60606060
; AVX: # %bb.0: # %entry
60616061
; AVX-NEXT: vroundpd $9, (%rdi), %xmm0
60626062
; AVX-NEXT: retq
@@ -6068,8 +6068,8 @@ entry:
60686068
ret <2 x double> %floor
60696069
}
60706070

6071-
define <3 x float> @constrained_vector_floor_v3f32(ptr %a) #0 {
6072-
; CHECK-LABEL: constrained_vector_floor_v3f32:
6071+
define <3 x float> @constrained_vector_floor_v3f32_var(ptr %a) #0 {
6072+
; CHECK-LABEL: constrained_vector_floor_v3f32_var:
60736073
; CHECK: # %bb.0: # %entry
60746074
; CHECK-NEXT: subq $56, %rsp
60756075
; CHECK-NEXT: .cfi_def_cfa_offset 64
@@ -6092,7 +6092,7 @@ define <3 x float> @constrained_vector_floor_v3f32(ptr %a) #0 {
60926092
; CHECK-NEXT: .cfi_def_cfa_offset 8
60936093
; CHECK-NEXT: retq
60946094
;
6095-
; AVX-LABEL: constrained_vector_floor_v3f32:
6095+
; AVX-LABEL: constrained_vector_floor_v3f32_var:
60966096
; AVX: # %bb.0: # %entry
60976097
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
60986098
; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm0
@@ -6111,8 +6111,8 @@ entry:
61116111
ret <3 x float> %floor
61126112
}
61136113

6114-
define <3 x double> @constrained_vector_floor_v3f64(ptr %a) #0 {
6115-
; CHECK-LABEL: constrained_vector_floor_v3f64:
6114+
define <3 x double> @constrained_vector_floor_v3f64_var(ptr %a) #0 {
6115+
; CHECK-LABEL: constrained_vector_floor_v3f64_var:
61166116
; CHECK: # %bb.0: # %entry
61176117
; CHECK-NEXT: subq $40, %rsp
61186118
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -6140,7 +6140,7 @@ define <3 x double> @constrained_vector_floor_v3f64(ptr %a) #0 {
61406140
; CHECK-NEXT: .cfi_def_cfa_offset 8
61416141
; CHECK-NEXT: retq
61426142
;
6143-
; AVX-LABEL: constrained_vector_floor_v3f64:
6143+
; AVX-LABEL: constrained_vector_floor_v3f64_var:
61446144
; AVX: # %bb.0: # %entry
61456145
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
61466146
; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm0
@@ -6155,8 +6155,8 @@ entry:
61556155
ret <3 x double> %floor
61566156
}
61576157

6158-
define <1 x float> @constrained_vector_round_v1f32(ptr %a) #0 {
6159-
; CHECK-LABEL: constrained_vector_round_v1f32:
6158+
define <1 x float> @constrained_vector_round_v1f32_var(ptr %a) #0 {
6159+
; CHECK-LABEL: constrained_vector_round_v1f32_var:
61606160
; CHECK: # %bb.0: # %entry
61616161
; CHECK-NEXT: pushq %rax
61626162
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -6166,7 +6166,7 @@ define <1 x float> @constrained_vector_round_v1f32(ptr %a) #0 {
61666166
; CHECK-NEXT: .cfi_def_cfa_offset 8
61676167
; CHECK-NEXT: retq
61686168
;
6169-
; AVX-LABEL: constrained_vector_round_v1f32:
6169+
; AVX-LABEL: constrained_vector_round_v1f32_var:
61706170
; AVX: # %bb.0: # %entry
61716171
; AVX-NEXT: pushq %rax
61726172
; AVX-NEXT: .cfi_def_cfa_offset 16
@@ -6183,8 +6183,8 @@ entry:
61836183
ret <1 x float> %round
61846184
}
61856185

6186-
define <2 x double> @constrained_vector_round_v2f64(ptr %a) #0 {
6187-
; CHECK-LABEL: constrained_vector_round_v2f64:
6186+
define <2 x double> @constrained_vector_round_v2f64_var(ptr %a) #0 {
6187+
; CHECK-LABEL: constrained_vector_round_v2f64_var:
61886188
; CHECK: # %bb.0: # %entry
61896189
; CHECK-NEXT: subq $40, %rsp
61906190
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -6202,7 +6202,7 @@ define <2 x double> @constrained_vector_round_v2f64(ptr %a) #0 {
62026202
; CHECK-NEXT: .cfi_def_cfa_offset 8
62036203
; CHECK-NEXT: retq
62046204
;
6205-
; AVX-LABEL: constrained_vector_round_v2f64:
6205+
; AVX-LABEL: constrained_vector_round_v2f64_var:
62066206
; AVX: # %bb.0: # %entry
62076207
; AVX-NEXT: subq $40, %rsp
62086208
; AVX-NEXT: .cfi_def_cfa_offset 48
@@ -6227,8 +6227,8 @@ entry:
62276227
ret <2 x double> %round
62286228
}
62296229

6230-
define <3 x float> @constrained_vector_round_v3f32(ptr %a) #0 {
6231-
; CHECK-LABEL: constrained_vector_round_v3f32:
6230+
define <3 x float> @constrained_vector_round_v3f32_var(ptr %a) #0 {
6231+
; CHECK-LABEL: constrained_vector_round_v3f32_var:
62326232
; CHECK: # %bb.0: # %entry
62336233
; CHECK-NEXT: subq $56, %rsp
62346234
; CHECK-NEXT: .cfi_def_cfa_offset 64
@@ -6251,7 +6251,7 @@ define <3 x float> @constrained_vector_round_v3f32(ptr %a) #0 {
62516251
; CHECK-NEXT: .cfi_def_cfa_offset 8
62526252
; CHECK-NEXT: retq
62536253
;
6254-
; AVX-LABEL: constrained_vector_round_v3f32:
6254+
; AVX-LABEL: constrained_vector_round_v3f32_var:
62556255
; AVX: # %bb.0: # %entry
62566256
; AVX-NEXT: pushq %rbx
62576257
; AVX-NEXT: .cfi_def_cfa_offset 16
@@ -6288,8 +6288,8 @@ entry:
62886288
}
62896289

62906290

6291-
define <3 x double> @constrained_vector_round_v3f64(ptr %a) #0 {
6292-
; CHECK-LABEL: constrained_vector_round_v3f64:
6291+
define <3 x double> @constrained_vector_round_v3f64_var(ptr %a) #0 {
6292+
; CHECK-LABEL: constrained_vector_round_v3f64_var:
62936293
; CHECK: # %bb.0: # %entry
62946294
; CHECK-NEXT: subq $40, %rsp
62956295
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -6317,7 +6317,7 @@ define <3 x double> @constrained_vector_round_v3f64(ptr %a) #0 {
63176317
; CHECK-NEXT: .cfi_def_cfa_offset 8
63186318
; CHECK-NEXT: retq
63196319
;
6320-
; AVX-LABEL: constrained_vector_round_v3f64:
6320+
; AVX-LABEL: constrained_vector_round_v3f64_var:
63216321
; AVX: # %bb.0: # %entry
63226322
; AVX-NEXT: pushq %rbx
63236323
; AVX-NEXT: .cfi_def_cfa_offset 16
@@ -6354,8 +6354,8 @@ entry:
63546354
ret <3 x double> %round
63556355
}
63566356

6357-
define <1 x float> @constrained_vector_trunc_v1f32(ptr %a) #0 {
6358-
; CHECK-LABEL: constrained_vector_trunc_v1f32:
6357+
define <1 x float> @constrained_vector_trunc_v1f32_var(ptr %a) #0 {
6358+
; CHECK-LABEL: constrained_vector_trunc_v1f32_var:
63596359
; CHECK: # %bb.0: # %entry
63606360
; CHECK-NEXT: pushq %rax
63616361
; CHECK-NEXT: .cfi_def_cfa_offset 16
@@ -6365,7 +6365,7 @@ define <1 x float> @constrained_vector_trunc_v1f32(ptr %a) #0 {
63656365
; CHECK-NEXT: .cfi_def_cfa_offset 8
63666366
; CHECK-NEXT: retq
63676367
;
6368-
; AVX-LABEL: constrained_vector_trunc_v1f32:
6368+
; AVX-LABEL: constrained_vector_trunc_v1f32_var:
63696369
; AVX: # %bb.0: # %entry
63706370
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
63716371
; AVX-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
@@ -6378,8 +6378,8 @@ entry:
63786378
ret <1 x float> %trunc
63796379
}
63806380

6381-
define <2 x double> @constrained_vector_trunc_v2f64(ptr %a) #0 {
6382-
; CHECK-LABEL: constrained_vector_trunc_v2f64:
6381+
define <2 x double> @constrained_vector_trunc_v2f64_var(ptr %a) #0 {
6382+
; CHECK-LABEL: constrained_vector_trunc_v2f64_var:
63836383
; CHECK: # %bb.0: # %entry
63846384
; CHECK-NEXT: subq $40, %rsp
63856385
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -6397,7 +6397,7 @@ define <2 x double> @constrained_vector_trunc_v2f64(ptr %a) #0 {
63976397
; CHECK-NEXT: .cfi_def_cfa_offset 8
63986398
; CHECK-NEXT: retq
63996399
;
6400-
; AVX-LABEL: constrained_vector_trunc_v2f64:
6400+
; AVX-LABEL: constrained_vector_trunc_v2f64_var:
64016401
; AVX: # %bb.0: # %entry
64026402
; AVX-NEXT: vroundpd $11, (%rdi), %xmm0
64036403
; AVX-NEXT: retq
@@ -6409,8 +6409,8 @@ entry:
64096409
ret <2 x double> %trunc
64106410
}
64116411

6412-
define <3 x float> @constrained_vector_trunc_v3f32(ptr %a) #0 {
6413-
; CHECK-LABEL: constrained_vector_trunc_v3f32:
6412+
define <3 x float> @constrained_vector_trunc_v3f32_var(ptr %a) #0 {
6413+
; CHECK-LABEL: constrained_vector_trunc_v3f32_var:
64146414
; CHECK: # %bb.0: # %entry
64156415
; CHECK-NEXT: subq $56, %rsp
64166416
; CHECK-NEXT: .cfi_def_cfa_offset 64
@@ -6433,7 +6433,7 @@ define <3 x float> @constrained_vector_trunc_v3f32(ptr %a) #0 {
64336433
; CHECK-NEXT: .cfi_def_cfa_offset 8
64346434
; CHECK-NEXT: retq
64356435
;
6436-
; AVX-LABEL: constrained_vector_trunc_v3f32:
6436+
; AVX-LABEL: constrained_vector_trunc_v3f32_var:
64376437
; AVX: # %bb.0: # %entry
64386438
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
64396439
; AVX-NEXT: vroundss $11, %xmm0, %xmm0, %xmm0
@@ -6452,8 +6452,8 @@ entry:
64526452
ret <3 x float> %trunc
64536453
}
64546454

6455-
define <3 x double> @constrained_vector_trunc_v3f64(ptr %a) #0 {
6456-
; CHECK-LABEL: constrained_vector_trunc_v3f64:
6455+
define <3 x double> @constrained_vector_trunc_v3f64_var(ptr %a) #0 {
6456+
; CHECK-LABEL: constrained_vector_trunc_v3f64_var:
64576457
; CHECK: # %bb.0: # %entry
64586458
; CHECK-NEXT: subq $40, %rsp
64596459
; CHECK-NEXT: .cfi_def_cfa_offset 48
@@ -6481,7 +6481,7 @@ define <3 x double> @constrained_vector_trunc_v3f64(ptr %a) #0 {
64816481
; CHECK-NEXT: .cfi_def_cfa_offset 8
64826482
; CHECK-NEXT: retq
64836483
;
6484-
; AVX-LABEL: constrained_vector_trunc_v3f64:
6484+
; AVX-LABEL: constrained_vector_trunc_v3f64_var:
64856485
; AVX: # %bb.0: # %entry
64866486
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
64876487
; AVX-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0

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