move CV_SHUFFLE_SCI_B expansion from RISCVExpandPseudoInsts.cpp to RISCVISelLowering.cpp

Author: realqhc

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

@@ -56,8 +56,6 @@ class RISCVExpandPseudo : public MachineFunctionPass {
                             MachineBasicBlock::iterator MBBI);
   bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI);
-  bool expandVendorXcvsimdShuffle(MachineBasicBlock &MBB,
-                                  MachineBasicBlock::iterator MBBI);
 #ifndef NDEBUG
   unsigned getInstSizeInBytes(const MachineFunction &MF) const {
     unsigned Size = 0;
@@ -166,8 +164,6 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
   case RISCV::PseudoVMSET_M_B64:
     // vmset.m vd => vmxnor.mm vd, vd, vd
     return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
-  case RISCV::CV_SHUFFLE_SCI_B_PSEUDO:
-    return expandVendorXcvsimdShuffle(MBB, MBBI);
   }
 
   return false;
@@ -419,23 +415,6 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
   return true;
 }
 
-bool RISCVExpandPseudo::expandVendorXcvsimdShuffle(
-    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
-  DebugLoc DL = MBBI->getDebugLoc();
-  Register DstReg = MBBI->getOperand(0).getReg();
-  Register SrcReg = MBBI->getOperand(1).getReg();
-  uint8_t Imm = MBBI->getOperand(2).getImm();
-  const unsigned Opcodes[] = {
-      RISCV::CV_SHUFFLEI0_SCI_B, RISCV::CV_SHUFFLEI1_SCI_B,
-      RISCV::CV_SHUFFLEI2_SCI_B, RISCV::CV_SHUFFLEI3_SCI_B};
-  const MCInstrDesc &Desc = TII->get(Opcodes[Imm >> 6]);
-  BuildMI(MBB, MBBI, DL, Desc, DstReg)
-      .addReg(SrcReg)
-      .addImm(APInt(6, Imm, true).getSExtValue());
-  MBBI->eraseFromParent();
-  return true;
-}
-
 class RISCVPreRAExpandPseudo : public MachineFunctionPass {
 public:
   const RISCVSubtarget *STI;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -20393,6 +20393,8 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return emitFROUND(MI, BB, Subtarget);
   case RISCV::PROBED_STACKALLOC_DYN:
     return emitDynamicProbedAlloc(MI, BB);
+  case RISCV::PseudoCV_SHUFFLE_SCI_B:
+    return emitCV_SHUFFLE_SCI_B(MI, BB, Subtarget);
   case TargetOpcode::STATEPOINT:
     // STATEPOINT is a pseudo instruction which has no implicit defs/uses
     // while jal call instruction (where statepoint will be lowered at the end)

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

@@ -1052,9 +1052,9 @@ let Predicates = [HasVendorXCVsimd] in {
 
   defm SHUFFLE : PatCorevGprGprHB<"shuffle">;
   def : PatCorevGprTImm<"shuffle_sci_h", "SHUFFLE_SCI_H">;
-
-  def CV_SHUFFLE_SCI_B_PSEUDO : Pseudo<(outs GPR:$rd), (ins GPR:$rs, cv_imm8:$imm), []>;
-  def : PatGprImm<int_riscv_cv_simd_shuffle_sci_b, CV_SHUFFLE_SCI_B_PSEUDO, cv_imm8>;
+  let usesCustomInserter = 1 in
+  def PseudoCV_SHUFFLE_SCI_B : Pseudo<(outs GPR:$rd), (ins GPR:$rs, cv_imm8:$imm), []>;
+  def : PatGprImm<int_riscv_cv_simd_shuffle_sci_b, PseudoCV_SHUFFLE_SCI_B, cv_imm8>;
 
   def : Pat<(int_riscv_cv_simd_shuffle2_h GPR:$rs1, GPR:$rs2, GPR:$rd),
             (CV_SHUFFLE2_H GPR:$rd, GPR:$rs1, GPR:$rs2)>;