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[FMV][AArch64] Unify features memtag and memtag2. (#112511)
If we split these features in the compiler (see relevant pull request #109299), we would only be able to hand-write a 'memtag2' version using inline assembly since the compiler cannot generate the instructions that become available with FEAT_MTE2. However these instructions only work at Exception Level 1, so they would be unusable since FMV is a user space facility. I am therefore unifying them. Approved in ACLE as ARM-software/acle#351
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-40
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12 files changed

+39
-40
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‎clang/include/clang/Basic/AttrDocs.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2669,7 +2669,7 @@ sign. For example:
26692669

26702670
.. code-block:: c++
26712671

2672-
__attribute__((target_clones("sha2+memtag2", "fcma+sve2-pmull128")))
2672+
__attribute__((target_clones("sha2+memtag", "fcma+sve2-pmull128")))
26732673
void foo() {}
26742674

26752675
For every multiversioned function a ``default`` (fallback) implementation

‎clang/lib/Basic/Targets/AArch64.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -784,7 +784,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
784784
.Case("sme-fa64", HasSMEFA64)
785785
.Case("sme-f16f16", HasSMEF16F16)
786786
.Case("sme-b16b16", HasSMEB16B16)
787-
.Cases("memtag", "memtag2", HasMTE)
787+
.Case("memtag", HasMTE)
788788
.Case("sb", HasSB)
789789
.Case("predres", HasPredRes)
790790
.Cases("ssbs", "ssbs2", HasSSBS)

‎clang/test/CodeGen/aarch64-cpu-supports-target.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ int check_all_feature() {
1717
return 7;
1818
else if (__builtin_cpu_supports("sve2-bitperm+sve2-sha3+sve2-sm4"))
1919
return 8;
20-
else if (__builtin_cpu_supports("sme+memtag+memtag2+memtag3+sb"))
20+
else if (__builtin_cpu_supports("sme+memtag+memtag3+sb"))
2121
return 9;
2222
else if (__builtin_cpu_supports("predres+ssbs+ssbs2+bti+ls64+ls64_v"))
2323
return 10;

‎clang/test/CodeGen/aarch64-cpu-supports.c‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
1-
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --version 2
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --global-value-regex ".*"
22
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
33

4+
//.
45
// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
5-
// CHECK-LABEL: define dso_local i32 @main
6-
// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
6+
//.
7+
// CHECK-LABEL: @main(
78
// CHECK-NEXT: entry:
89
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
910
// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
@@ -17,8 +18,8 @@
1718
// CHECK-NEXT: br label [[RETURN:%.*]]
1819
// CHECK: if.end:
1920
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
20-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 9070970929152
21-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 9070970929152
21+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17867063951360
22+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17867063951360
2223
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
2324
// CHECK-NEXT: br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
2425
// CHECK: if.then1:
@@ -60,3 +61,7 @@ int main(void) {
6061

6162
return 0;
6263
}
64+
//.
65+
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
66+
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
67+
//.

‎clang/test/CodeGen/aarch64-fmv-dependencies.c‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -72,13 +72,10 @@ __attribute__((target_version("ls64"))) int fmv(void) { return 0; }
7272
// CHECK: define dso_local i32 @fmv._Mlse() #[[lse:[0-9]+]] {
7373
__attribute__((target_version("lse"))) int fmv(void) { return 0; }
7474

75-
// CHECK: define dso_local i32 @fmv._Mmemtag() #[[ATTR0:[0-9]+]] {
75+
// CHECK: define dso_local i32 @fmv._Mmemtag() #[[memtag:[0-9]+]] {
7676
__attribute__((target_version("memtag"))) int fmv(void) { return 0; }
7777

78-
// CHECK: define dso_local i32 @fmv._Mmemtag2() #[[memtag2:[0-9]+]] {
79-
__attribute__((target_version("memtag2"))) int fmv(void) { return 0; }
80-
81-
// CHECK: define dso_local i32 @fmv._Mmemtag3() #[[memtag2:[0-9]+]] {
78+
// CHECK: define dso_local i32 @fmv._Mmemtag3() #[[memtag:[0-9]+]] {
8279
__attribute__((target_version("memtag3"))) int fmv(void) { return 0; }
8380

8481
// CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] {
@@ -200,7 +197,7 @@ int caller() {
200197
// CHECK: attributes #[[jscvt]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a"
201198
// CHECK: attributes #[[ls64]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
202199
// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
203-
// CHECK: attributes #[[memtag2]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
200+
// CHECK: attributes #[[memtag]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
204201
// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
205202
// CHECK: attributes #[[pmull]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
206203
// CHECK: attributes #[[predres]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a"

‎clang/test/CodeGen/attr-target-clones-aarch64.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +mte -target-feature +bti -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-MTE-BTI
55

66
int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
7-
int __attribute__((target_clones("sha2", "sha2+memtag2", " default "))) ftc_def(void) { return 1; }
7+
int __attribute__((target_clones("sha2", "sha2+memtag", " default "))) ftc_def(void) { return 1; }
88
int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; }
99
int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; }
10-
int __attribute__((target_clones("memtag2", "bti"))) ftc_dup3(void) { return 4; }
10+
int __attribute__((target_clones("memtag", "bti"))) ftc_dup3(void) { return 4; }
1111
int foo() {
1212
return ftc() + ftc_def() + ftc_dup1() + ftc_dup2() + ftc_dup3();
1313
}
@@ -90,7 +90,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
9090
//
9191
//
9292
// CHECK: Function Attrs: noinline nounwind optnone
93-
// CHECK-LABEL: define {{[^@]+}}@ftc_def._Mmemtag2Msha2
93+
// CHECK-LABEL: define {{[^@]+}}@ftc_def._MmemtagMsha2
9494
// CHECK-SAME: () #[[ATTR3:[0-9]+]] {
9595
// CHECK-NEXT: entry:
9696
// CHECK-NEXT: ret i32 1
@@ -105,7 +105,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
105105
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
106106
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
107107
// CHECK: resolver_return:
108-
// CHECK-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
108+
// CHECK-NEXT: ret ptr @ftc_def._MmemtagMsha2
109109
// CHECK: resolver_else:
110110
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
111111
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
@@ -176,7 +176,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
176176
//
177177
//
178178
// CHECK: Function Attrs: noinline nounwind optnone
179-
// CHECK-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag2
179+
// CHECK-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag
180180
// CHECK-SAME: () #[[ATTR6:[0-9]+]] {
181181
// CHECK-NEXT: entry:
182182
// CHECK-NEXT: ret i32 4
@@ -206,7 +206,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
206206
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
207207
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
208208
// CHECK: resolver_return1:
209-
// CHECK-NEXT: ret ptr @ftc_dup3._Mmemtag2
209+
// CHECK-NEXT: ret ptr @ftc_dup3._Mmemtag
210210
// CHECK: resolver_else2:
211211
// CHECK-NEXT: ret ptr @ftc_dup3.default
212212
//
@@ -547,7 +547,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
547547
//
548548
//
549549
// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone
550-
// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def._Mmemtag2Msha2
550+
// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_def._MmemtagMsha2
551551
// CHECK-MTE-BTI-SAME: () #[[ATTR2]] {
552552
// CHECK-MTE-BTI-NEXT: entry:
553553
// CHECK-MTE-BTI-NEXT: ret i32 1
@@ -562,7 +562,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
562562
// CHECK-MTE-BTI-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
563563
// CHECK-MTE-BTI-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
564564
// CHECK-MTE-BTI: resolver_return:
565-
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
565+
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_def._MmemtagMsha2
566566
// CHECK-MTE-BTI: resolver_else:
567567
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
568568
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
@@ -633,7 +633,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
633633
//
634634
//
635635
// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone
636-
// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag2
636+
// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_dup3._Mmemtag
637637
// CHECK-MTE-BTI-SAME: () #[[ATTR5:[0-9]+]] {
638638
// CHECK-MTE-BTI-NEXT: entry:
639639
// CHECK-MTE-BTI-NEXT: ret i32 4
@@ -663,7 +663,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
663663
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
664664
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
665665
// CHECK-MTE-BTI: resolver_return1:
666-
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mmemtag2
666+
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3._Mmemtag
667667
// CHECK-MTE-BTI: resolver_else2:
668668
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_dup3.default
669669
//

‎clang/test/CodeGen/attr-target-version.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { re
3434
inline int __attribute__((target_version("sve+sve-bf16"))) fmv_inline(void) { return 4; }
3535
inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
3636
inline int __attribute__((target_version("sve2+sve2-pmull128+sve2-bitperm"))) fmv_inline(void) { return 9; }
37-
inline int __attribute__((target_version("sve2-sm4+memtag2"))) fmv_inline(void) { return 10; }
37+
inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
3838
inline int __attribute__((target_version("memtag3+rcpc3+mops"))) fmv_inline(void) { return 11; }
3939
inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; }
4040
inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; }
@@ -500,8 +500,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
500500
// CHECK-NEXT: ret ptr @fmv._McrcMls64
501501
// CHECK: resolver_else6:
502502
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
503-
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 8796093022216
504-
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 8796093022216
503+
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17592186044424
504+
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17592186044424
505505
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
506506
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
507507
// CHECK: resolver_return7:
@@ -729,7 +729,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
729729
//
730730
//
731731
// CHECK: Function Attrs: noinline nounwind optnone
732-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag2Msve2-sm4
732+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4
733733
// CHECK-SAME: () #[[ATTR34:[0-9]+]] {
734734
// CHECK-NEXT: entry:
735735
// CHECK-NEXT: ret i32 10
@@ -751,21 +751,21 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
751751
//
752752
// CHECK: Function Attrs: noinline nounwind optnone
753753
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd
754-
// CHECK-SAME: () #[[ATTR4]] {
754+
// CHECK-SAME: () #[[ATTR36:[0-9]+]] {
755755
// CHECK-NEXT: entry:
756756
// CHECK-NEXT: ret i32 14
757757
//
758758
//
759759
// CHECK: Function Attrs: noinline nounwind optnone
760760
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4
761-
// CHECK-SAME: () #[[ATTR36:[0-9]+]] {
761+
// CHECK-SAME: () #[[ATTR37:[0-9]+]] {
762762
// CHECK-NEXT: entry:
763763
// CHECK-NEXT: ret i32 15
764764
//
765765
//
766766
// CHECK: Function Attrs: noinline nounwind optnone
767767
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm
768-
// CHECK-SAME: () #[[ATTR37:[0-9]+]] {
768+
// CHECK-SAME: () #[[ATTR38:[0-9]+]] {
769769
// CHECK-NEXT: entry:
770770
// CHECK-NEXT: ret i32 16
771771
//
@@ -826,7 +826,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
826826
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
827827
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
828828
// CHECK: resolver_return9:
829-
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag2Msve2-sm4
829+
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4
830830
// CHECK: resolver_else10:
831831
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
832832
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1236950581248

‎clang/test/Sema/attr-target-clones-aarch64.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
2222
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
2323
// expected-note@-2 {{previous declaration is here}}
2424
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
25-
int __attribute__((target_clones("dgh+memtag+rpres", "ebf16+dpb", "default"))) redecl4(void) { return 1; }
25+
int __attribute__((target_clones("dgh+rpres", "ebf16+dpb", "default"))) redecl4(void) { return 1; }
2626

2727
int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
2828
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ enum CPUFeatures {
6565
FEAT_SVE_SHA3,
6666
FEAT_SVE_SM4,
6767
FEAT_SME,
68-
FEAT_MEMTAG,
68+
RESERVED_FEAT_MEMTAG, // previously used and now ABI legacy
6969
FEAT_MEMTAG2,
7070
FEAT_MEMTAG3,
7171
FEAT_SB,

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,8 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
4545
setCPUFeature(FEAT_SB);
4646
if (hwcap & HWCAP_SSBS)
4747
setCPUFeature(FEAT_SSBS2);
48-
if (hwcap2 & HWCAP2_MTE) {
49-
setCPUFeature(FEAT_MEMTAG);
48+
if (hwcap2 & HWCAP2_MTE)
5049
setCPUFeature(FEAT_MEMTAG2);
51-
}
5250
if (hwcap2 & HWCAP2_MTE3)
5351
setCPUFeature(FEAT_MEMTAG3);
5452
if (hwcap2 & HWCAP2_SVEAES)

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