Update sme test with +i8mm

Author: NickGuy-Arm

llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mattr=+dotprod,+i8mm -aarch64-enable-partial-reduce-nodes=true < %s | FileCheck %s --check-prefixes=COMMON,NEON
 ; RUN: llc -mattr=+sve,+dotprod,+i8mm -aarch64-enable-partial-reduce-nodes=true < %s | FileCheck %s --check-prefixes=COMMON,SVE
-; RUN: llc -mattr=+sme -aarch64-enable-partial-reduce-nodes=true -force-streaming < %s | FileCheck %s --check-prefix=SME
+; RUN: llc -mattr=+sme,+i8mm -aarch64-enable-partial-reduce-nodes=true -force-streaming < %s | FileCheck %s --check-prefix=SME
 
 target triple = "aarch64"
 
@@ -418,23 +418,10 @@ define <4 x i32> @four_way_i8_i32_vl128_usdot(ptr %accptr, ptr %uptr, ptr %sptr)
 ;
 ; SME-LABEL: four_way_i8_i32_vl128_usdot:
 ; SME:       // %bb.0:
-; SME-NEXT:    ptrue p0.s, vl4
-; SME-NEXT:    ldr q2, [x0]
-; SME-NEXT:    mov w8, #4 // =0x4
-; SME-NEXT:    ld1b { z0.s }, p0/z, [x1]
-; SME-NEXT:    ld1sb { z1.s }, p0/z, [x2]
-; SME-NEXT:    mad z0.s, p0/m, z1.s, z2.s
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1, x8]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2, x8]
-; SME-NEXT:    mov w8, #8 // =0x8
-; SME-NEXT:    mla z0.s, p0/m, z2.s, z1.s
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1, x8]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2, x8]
-; SME-NEXT:    mov w8, #12 // =0xc
-; SME-NEXT:    mla z0.s, p0/m, z2.s, z1.s
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1, x8]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2, x8]
-; SME-NEXT:    mla z0.s, p0/m, z2.s, z1.s
+; SME-NEXT:    ldr q0, [x0]
+; SME-NEXT:    ldr q1, [x1]
+; SME-NEXT:    ldr q2, [x2]
+; SME-NEXT:    usdot z0.s, z1.b, z2.b
 ; SME-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; SME-NEXT:    ret
   %acc = load <4 x i32>, ptr %accptr
@@ -491,41 +478,11 @@ define <8 x i32> @four_way_i8_i32_vl128_double_width_usdot(ptr %accptr, ptr %upt
 ;
 ; SME-LABEL: four_way_i8_i32_vl128_double_width_usdot:
 ; SME:       // %bb.0:
-; SME-NEXT:    ptrue p0.s, vl4
-; SME-NEXT:    mov w8, #16 // =0x10
-; SME-NEXT:    mov w9, #4 // =0x4
-; SME-NEXT:    ldp q5, q4, [x0]
-; SME-NEXT:    ld1b { z0.s }, p0/z, [x1, x8]
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2, x8]
-; SME-NEXT:    ld1sb { z3.s }, p0/z, [x2]
-; SME-NEXT:    mov w8, #20 // =0x14
-; SME-NEXT:    ld1b { z6.s }, p0/z, [x1, x8]
-; SME-NEXT:    mad z0.s, p0/m, z2.s, z4.s
-; SME-NEXT:    ld1b { z2.s }, p0/z, [x1, x9]
-; SME-NEXT:    ld1sb { z4.s }, p0/z, [x2, x9]
-; SME-NEXT:    mad z1.s, p0/m, z3.s, z5.s
-; SME-NEXT:    ld1sb { z3.s }, p0/z, [x2, x8]
-; SME-NEXT:    mov w8, #24 // =0x18
-; SME-NEXT:    mov w9, #8 // =0x8
-; SME-NEXT:    ld1b { z5.s }, p0/z, [x1, x8]
-; SME-NEXT:    mla z0.s, p0/m, z3.s, z6.s
-; SME-NEXT:    ld1sb { z3.s }, p0/z, [x2, x8]
-; SME-NEXT:    mov w8, #28 // =0x1c
-; SME-NEXT:    mla z1.s, p0/m, z4.s, z2.s
-; SME-NEXT:    ld1b { z2.s }, p0/z, [x1, x9]
-; SME-NEXT:    ld1sb { z4.s }, p0/z, [x2, x9]
-; SME-NEXT:    mov w9, #12 // =0xc
-; SME-NEXT:    ld1b { z6.s }, p0/z, [x1, x8]
-; SME-NEXT:    mla z1.s, p0/m, z4.s, z2.s
-; SME-NEXT:    movprfx z2, z0
-; SME-NEXT:    mla z2.s, p0/m, z3.s, z5.s
-; SME-NEXT:    ld1b { z0.s }, p0/z, [x1, x9]
-; SME-NEXT:    ld1sb { z3.s }, p0/z, [x2, x8]
-; SME-NEXT:    ld1sb { z4.s }, p0/z, [x2, x9]
-; SME-NEXT:    mad z0.s, p0/m, z4.s, z1.s
-; SME-NEXT:    movprfx z1, z2
-; SME-NEXT:    mla z1.s, p0/m, z3.s, z6.s
+; SME-NEXT:    ldp q0, q1, [x0]
+; SME-NEXT:    ldp q3, q2, [x1]
+; SME-NEXT:    ldp q5, q4, [x2]
+; SME-NEXT:    usdot z0.s, z3.b, z5.b
+; SME-NEXT:    usdot z1.s, z2.b, z4.b
 ; SME-NEXT:    // kill: def $q0 killed $q0 killed $z0
 ; SME-NEXT:    // kill: def $q1 killed $q1 killed $z1
 ; SME-NEXT:    ret
@@ -610,20 +567,10 @@ define <8 x i32> @four_way_i8_i32_vl256_usdot(ptr %accptr, ptr %uptr, ptr %sptr)
 ;
 ; SME-LABEL: four_way_i8_i32_vl256_usdot:
 ; SME:       // %bb.0:
-; SME-NEXT:    ptrue p0.s
 ; SME-NEXT:    ldr z0, [x0]
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2]
-; SME-NEXT:    mla z0.s, p0/m, z2.s, z1.s
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1, #1, mul vl]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2, #1, mul vl]
-; SME-NEXT:    mla z0.s, p0/m, z2.s, z1.s
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1, #2, mul vl]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2, #2, mul vl]
-; SME-NEXT:    mla z0.s, p0/m, z2.s, z1.s
-; SME-NEXT:    ld1b { z1.s }, p0/z, [x1, #3, mul vl]
-; SME-NEXT:    ld1sb { z2.s }, p0/z, [x2, #3, mul vl]
-; SME-NEXT:    mla z0.s, p0/m, z2.s, z1.s
+; SME-NEXT:    ldr z1, [x1]
+; SME-NEXT:    ldr z2, [x2]
+; SME-NEXT:    usdot z0.s, z1.b, z2.b
 ; SME-NEXT:    mov z1.d, z0.d
 ; SME-NEXT:    ext z1.b, z1.b, z0.b, #16
 ; SME-NEXT:    // kill: def $q0 killed $q0 killed $z0