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1 parent 3b6e255 commit b7017efCopy full SHA for b7017ef
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -665,4 +665,4 @@ def FRM : RISCVReg<0, "frm">;
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def SSP : RISCVReg<0, "ssp">;
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// Dummy SiFive VCIX state register
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-def SF_VCIX_STATE : RISCVReg<0, "sf_vcix_state">;
+def SF_VCIX_STATE : RISCVReg<0, "sf.vcix_state">;
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