[AArch64][GlobalISel] Add test coverage for more adc / ands instructions. NFC

Author: davemgreen

llvm/test/CodeGen/AArch64/adc.ll

@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefix=CHECK-LE %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK-BE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefixes=CHECK-LE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefixes=CHECK-BE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 -global-isel | FileCheck --check-prefixes=CHECK-GI %s
 
 define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
 ; CHECK-LE-LABEL: test_simple:
@@ -18,11 +19,16 @@ define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
 ; CHECK-BE-NEXT:    subs x1, x8, x5
 ; CHECK-BE-NEXT:    sbc x0, x9, x4
 ; CHECK-BE-NEXT:    ret
-
+;
+; CHECK-GI-LABEL: test_simple:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    adds x8, x0, x2
+; CHECK-GI-NEXT:    adc x9, x1, x3
+; CHECK-GI-NEXT:    subs x0, x8, x4
+; CHECK-GI-NEXT:    sbc x1, x9, x5
+; CHECK-GI-NEXT:    ret
   %valadd = add i128 %a, %b
-
   %valsub = sub i128 %valadd, %c
-
   ret i128 %valsub
 }
 
@@ -38,9 +44,13 @@ define i128 @test_imm(i128 %a) {
 ; CHECK-BE-NEXT:    adds x1, x1, #12
 ; CHECK-BE-NEXT:    cinc x0, x0, hs
 ; CHECK-BE-NEXT:    ret
-
+;
+; CHECK-GI-LABEL: test_imm:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    adds x0, x0, #12
+; CHECK-GI-NEXT:    adc x1, x1, xzr
+; CHECK-GI-NEXT:    ret
   %val = add i128 %a, 12
-
   ret i128 %val
 }
 
@@ -58,11 +68,16 @@ define i128 @test_shifted(i128 %a, i128 %b) {
 ; CHECK-BE-NEXT:    adds x1, x1, x3, lsl #45
 ; CHECK-BE-NEXT:    adc x0, x0, x8
 ; CHECK-BE-NEXT:    ret
-
+;
+; CHECK-GI-LABEL: test_shifted:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    lsr x8, x2, #19
+; CHECK-GI-NEXT:    adds x0, x0, x2, lsl #45
+; CHECK-GI-NEXT:    orr x8, x8, x3, lsl #45
+; CHECK-GI-NEXT:    adc x1, x1, x8
+; CHECK-GI-NEXT:    ret
   %rhs = shl i128 %b, 45
-
   %val = add i128 %a, %rhs
-
   ret i128 %val
 }
 
@@ -86,11 +101,19 @@ define i128 @test_extended(i128 %a, i16 %b) {
 ; CHECK-BE-NEXT:    extr x8, x9, x8, #61
 ; CHECK-BE-NEXT:    adc x0, x0, x8
 ; CHECK-BE-NEXT:    ret
-
+;
+; CHECK-GI-LABEL: test_extended:
+; CHECK-GI:       ; %bb.0:
+; CHECK-GI-NEXT:    ; kill: def $w2 killed $w2 def $x2
+; CHECK-GI-NEXT:    sxth x8, w2
+; CHECK-GI-NEXT:    adds x0, x0, w2, sxth #3
+; CHECK-GI-NEXT:    asr x9, x8, #63
+; CHECK-GI-NEXT:    lsr x8, x8, #61
+; CHECK-GI-NEXT:    orr x8, x8, x9, lsl #3
+; CHECK-GI-NEXT:    adc x1, x1, x8
+; CHECK-GI-NEXT:    ret
   %ext = sext i16 %b to i128
   %rhs = shl i128 %ext, 3
-
   %val = add i128 %a, %rhs
-
   ret i128 %val
 }

llvm/test/CodeGen/AArch64/addcarry-crash.ll

@@ -1,16 +1,29 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s | FileCheck %s
+; RUN: llc < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
 target triple = "arm64-apple-ios7.0"
 
 define i64 @foo(ptr nocapture readonly %ptr, i64 %a, i64 %b, i64 %c) local_unnamed_addr #0 {
-; CHECK-LABEL: foo:
-; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    lsr x8, x1, #32
-; CHECK-NEXT:    ldr w9, [x0, #4]
-; CHECK-NEXT:    cmn x3, x2
-; CHECK-NEXT:    umull x8, w9, w8
-; CHECK-NEXT:    cinc x0, x8, hs
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: foo:
+; CHECK-SD:       ; %bb.0: ; %entry
+; CHECK-SD-NEXT:    lsr x8, x1, #32
+; CHECK-SD-NEXT:    ldr w9, [x0, #4]
+; CHECK-SD-NEXT:    cmn x3, x2
+; CHECK-SD-NEXT:    umull x8, w9, w8
+; CHECK-SD-NEXT:    cinc x0, x8, hs
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: foo:
+; CHECK-GI:       ; %bb.0: ; %entry
+; CHECK-GI-NEXT:    ldr x8, [x0]
+; CHECK-GI-NEXT:    lsr x9, x1, #32
+; CHECK-GI-NEXT:    cmn x3, x2
+; CHECK-GI-NEXT:    cset w10, hs
+; CHECK-GI-NEXT:    lsr x8, x8, #32
+; CHECK-GI-NEXT:    and x10, x10, #0x1
+; CHECK-GI-NEXT:    umaddl x0, w8, w9, x10
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = lshr i64 %a, 32
   %1 = load i64, ptr %ptr, align 8
@@ -24,3 +37,6 @@ entry:
 }
 
 attributes #0 = { norecurse nounwind readonly }
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}

llvm/test/CodeGen/AArch64/arm64-vabs.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,CHECK-SD %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s -check-prefixes=CHECK,CHECK-SD
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {