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Signed-off-by: Sidorov, Dmitry <[email protected]>
1 parent 94cecfe commit b7591cf

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13 files changed

+101
-97
lines changed

13 files changed

+101
-97
lines changed

‎llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -689,10 +689,10 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
689689
const CallBase *CI = Info.CB;
690690
if (CI && CI->hasMetadata()) {
691691
if (MDNode *MD = CI->getMetadata(LLVMContext::MD_alias_scope))
692-
buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
692+
GR->buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
693693
SPIRV::Decoration::AliasScopeINTEL, MD);
694694
if (MDNode *MD = CI->getMetadata(LLVMContext::MD_noalias))
695-
buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
695+
GR->buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
696696
SPIRV::Decoration::NoAliasINTEL, MD);
697697
}
698698
}

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp‎

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1731,3 +1731,73 @@ LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
17311731
}
17321732
return LLT::scalar(64);
17331733
}
1734+
1735+
// Aliasing list MD contains several scope MD nodes whithin it. Each scope MD
1736+
// has a selfreference and an extra MD node for aliasing domain and also it
1737+
// can contain an optional string operand. Domain MD contains a self-reference
1738+
// with an optional string operand. Here we unfold the list, creating SPIR-V
1739+
// aliasing instructions.
1740+
// TODO: add support for an optional string operand.
1741+
MachineInstr *SPIRVGlobalRegistry::getOrAddMemAliasingINTELInst(
1742+
MachineIRBuilder &MIRBuilder, const MDNode *AliasingListMD) {
1743+
if (AliasingListMD->getNumOperands() == 0)
1744+
return nullptr;
1745+
if (auto L = AliasInstMDMap.find(AliasingListMD); L != AliasInstMDMap.end())
1746+
return L->second;
1747+
1748+
SmallVector<MachineInstr *> ScopeList;
1749+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1750+
for (const MDOperand &MDListOp : AliasingListMD->operands()) {
1751+
if (MDNode *ScopeMD = dyn_cast<MDNode>(MDListOp)) {
1752+
if (ScopeMD->getNumOperands() < 2)
1753+
return nullptr;
1754+
MDNode *DomainMD = dyn_cast<MDNode>(ScopeMD->getOperand(1));
1755+
if (!DomainMD)
1756+
return nullptr;
1757+
auto *Domain = [&] {
1758+
auto D = AliasInstMDMap.find(DomainMD);
1759+
if (D != AliasInstMDMap.end())
1760+
return D->second;
1761+
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
1762+
auto MIB =
1763+
MIRBuilder.buildInstr(SPIRV::OpAliasDomainDeclINTEL).addDef(Ret);
1764+
return MIB.getInstr();
1765+
}();
1766+
AliasInstMDMap.insert(std::make_pair(DomainMD, Domain));
1767+
auto *Scope = [&] {
1768+
auto S = AliasInstMDMap.find(ScopeMD);
1769+
if (S != AliasInstMDMap.end())
1770+
return S->second;
1771+
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
1772+
auto MIB = MIRBuilder.buildInstr(SPIRV::OpAliasScopeDeclINTEL)
1773+
.addDef(Ret)
1774+
.addUse(Domain->getOperand(0).getReg());
1775+
return MIB.getInstr();
1776+
}();
1777+
AliasInstMDMap.insert(std::make_pair(ScopeMD, Scope));
1778+
ScopeList.push_back(Scope);
1779+
}
1780+
}
1781+
1782+
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
1783+
auto MIB =
1784+
MIRBuilder.buildInstr(SPIRV::OpAliasScopeListDeclINTEL).addDef(Ret);
1785+
for (auto *Scope : ScopeList)
1786+
MIB.addUse(Scope->getOperand(0).getReg());
1787+
auto List = MIB.getInstr();
1788+
AliasInstMDMap.insert(std::make_pair(AliasingListMD, List));
1789+
return List;
1790+
}
1791+
1792+
void SPIRVGlobalRegistry::buildMemAliasingOpDecorate(
1793+
Register Reg, MachineIRBuilder &MIRBuilder, uint32_t Dec,
1794+
const MDNode *AliasingListMD) {
1795+
MachineInstr *AliasList =
1796+
getOrAddMemAliasingINTELInst(MIRBuilder, AliasingListMD);
1797+
if (!AliasList)
1798+
return;
1799+
MIRBuilder.buildInstr(SPIRV::OpDecorate)
1800+
.addUse(Reg)
1801+
.addImm(Dec)
1802+
.addUse(AliasList->getOperand(0).getReg());
1803+
}

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,9 @@ class SPIRVGlobalRegistry {
9292
// Maps OpVariable and OpFunction-related v-regs to its LLVM IR definition.
9393
DenseMap<std::pair<const MachineFunction *, Register>, const Value *> Reg2GO;
9494

95+
// map of aliasing decorations to aliasing metadata
96+
std::unordered_map<const MDNode *, MachineInstr *> AliasInstMDMap;
97+
9598
// Add a new OpTypeXXX instruction without checking for duplicates.
9699
SPIRVType *createSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
97100
SPIRV::AccessQualifier::AccessQualifier AQ =
@@ -620,6 +623,11 @@ class SPIRVGlobalRegistry {
620623

621624
const TargetRegisterClass *getRegClass(SPIRVType *SpvType) const;
622625
LLT getRegType(SPIRVType *SpvType) const;
626+
627+
MachineInstr *getOrAddMemAliasingINTELInst(MachineIRBuilder &MIRBuilder,
628+
const MDNode *AliasingListMD);
629+
void buildMemAliasingOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
630+
uint32_t Dec, const MDNode *GVarMD);
623631
};
624632
} // end namespace llvm
625633
#endif // LLLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1021,7 +1021,8 @@ bool SPIRVInstructionSelector::selectBitcast(Register ResVReg,
10211021

10221022
static void addMemoryOperands(MachineMemOperand *MemOp,
10231023
MachineInstrBuilder &MIB,
1024-
MachineIRBuilder &MIRBuilder) {
1024+
MachineIRBuilder &MIRBuilder,
1025+
SPIRVGlobalRegistry &GR) {
10251026
uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None);
10261027
if (MemOp->isVolatile())
10271028
SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile);
@@ -1036,13 +1037,13 @@ static void addMemoryOperands(MachineMemOperand *MemOp,
10361037
static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
10371038
if (ST->canUseExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing)) {
10381039
if (auto *MD = MemOp->getAAInfo().Scope) {
1039-
AliasList = getOrAddMemAliasingINTELInst(MIRBuilder, MD);
1040+
AliasList = GR.getOrAddMemAliasingINTELInst(MIRBuilder, MD);
10401041
if (AliasList)
10411042
SpvMemOp |=
10421043
static_cast<uint32_t>(SPIRV::MemoryOperand::AliasScopeINTELMask);
10431044
}
10441045
if (auto *MD = MemOp->getAAInfo().NoAlias) {
1045-
NoAliasList = getOrAddMemAliasingINTELInst(MIRBuilder, MD);
1046+
NoAliasList = GR.getOrAddMemAliasingINTELInst(MIRBuilder, MD);
10461047
if (NoAliasList)
10471048
SpvMemOp |=
10481049
static_cast<uint32_t>(SPIRV::MemoryOperand::NoAliasINTELMask);
@@ -1106,7 +1107,7 @@ bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
11061107
addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
11071108
} else {
11081109
MachineIRBuilder MIRBuilder(I);
1109-
addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder);
1110+
addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
11101111
}
11111112
return MIB.constrainAllUses(TII, TRI, RBI);
11121113
}
@@ -1149,7 +1150,7 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
11491150
addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
11501151
} else {
11511152
MachineIRBuilder MIRBuilder(I);
1152-
addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder);
1153+
addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
11531154
}
11541155
return MIB.constrainAllUses(TII, TRI, RBI);
11551156
}
@@ -1228,7 +1229,7 @@ bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
12281229
.addUse(I.getOperand(2).getReg());
12291230
if (I.getNumMemOperands()) {
12301231
MachineIRBuilder MIRBuilder(I);
1231-
addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder);
1232+
addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR);
12321233
}
12331234
Result &= MIB.constrainAllUses(TII, TRI, RBI);
12341235
if (ResVReg.isValid() && ResVReg != MIB->getOperand(0).getReg())

‎llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -809,7 +809,8 @@ static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
809809
insertInlineAsmProcess(MF, GR, ST, MIRBuilder, ToProcess);
810810
}
811811

812-
static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) {
812+
static void insertSpirvDecorations(MachineFunction &MF, SPIRVGlobalRegistry *GR,
813+
MachineIRBuilder MIB) {
813814
SmallVector<MachineInstr *, 10> ToErase;
814815
for (MachineBasicBlock &MBB : MF) {
815816
for (MachineInstr &MI : MBB) {
@@ -821,7 +822,7 @@ static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) {
821822
buildOpSpirvDecorations(MI.getOperand(1).getReg(), MIB,
822823
MI.getOperand(2).getMetadata());
823824
} else {
824-
buildMemAliasingOpDecorate(MI.getOperand(1).getReg(), MIB,
825+
GR->buildMemAliasingOpDecorate(MI.getOperand(1).getReg(), MIB,
825826
MI.getOperand(2).getImm(),
826827
MI.getOperand(3).getMetadata());
827828
}
@@ -1041,7 +1042,7 @@ bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) {
10411042

10421043
processInstrsWithTypeFolding(MF, GR, MIB);
10431044
removeImplicitFallthroughs(MF, MIB);
1044-
insertSpirvDecorations(MF, MIB);
1045+
insertSpirvDecorations(MF, GR, MIB);
10451046
insertInlineAsm(MF, GR, ST, MIB);
10461047
selectOpBitcasts(MF, GR, MIB);
10471048

‎llvm/lib/Target/SPIRV/SPIRVUtils.cpp‎

Lines changed: 0 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,6 @@
2828
#include <vector>
2929

3030
namespace llvm {
31-
// map of aliasing decorations to aliasing metadata
32-
std::unordered_map<const MDNode *, MachineInstr *> AliasInstMDMap;
3331

3432
// The following functions are used to add these string literals as a series of
3533
// 32-bit integer operands with the correct format, and unpack them if necessary
@@ -176,75 +174,6 @@ void buildOpSpirvDecorations(Register Reg, MachineIRBuilder &MIRBuilder,
176174
}
177175
}
178176

179-
// Aliasing list MD contains several scope MD nodes whithin it. Each scope MD
180-
// has a selfreference and an extra MD node for aliasing domain and also it
181-
// can contain an optional string operand. Domain MD contains a self-reference
182-
// with an optional string operand. Here we unfold the list, creating SPIR-V
183-
// aliasing instructions.
184-
// TODO: add support for an optional string operand.
185-
MachineInstr *getOrAddMemAliasingINTELInst(MachineIRBuilder &MIRBuilder,
186-
const MDNode *AliasingListMD) {
187-
if (AliasingListMD->getNumOperands() == 0)
188-
return nullptr;
189-
if (auto L = AliasInstMDMap.find(AliasingListMD); L != AliasInstMDMap.end())
190-
return L->second;
191-
192-
SmallVector<MachineInstr *> ScopeList;
193-
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
194-
for (const MDOperand &MDListOp : AliasingListMD->operands()) {
195-
if (MDNode *ScopeMD = dyn_cast<MDNode>(MDListOp)) {
196-
if (ScopeMD->getNumOperands() < 2)
197-
return nullptr;
198-
MDNode *DomainMD = dyn_cast<MDNode>(ScopeMD->getOperand(1));
199-
if (!DomainMD)
200-
return nullptr;
201-
auto *Domain = [&] {
202-
auto D = AliasInstMDMap.find(DomainMD);
203-
if (D != AliasInstMDMap.end())
204-
return D->second;
205-
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
206-
auto MIB =
207-
MIRBuilder.buildInstr(SPIRV::OpAliasDomainDeclINTEL).addDef(Ret);
208-
return MIB.getInstr();
209-
}();
210-
AliasInstMDMap.insert(std::make_pair(DomainMD, Domain));
211-
auto *Scope = [&] {
212-
auto S = AliasInstMDMap.find(ScopeMD);
213-
if (S != AliasInstMDMap.end())
214-
return S->second;
215-
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
216-
auto MIB = MIRBuilder.buildInstr(SPIRV::OpAliasScopeDeclINTEL)
217-
.addDef(Ret)
218-
.addUse(Domain->getOperand(0).getReg());
219-
return MIB.getInstr();
220-
}();
221-
AliasInstMDMap.insert(std::make_pair(ScopeMD, Scope));
222-
ScopeList.push_back(Scope);
223-
}
224-
}
225-
226-
const Register Ret = MRI->createVirtualRegister(&SPIRV::IDRegClass);
227-
auto MIB =
228-
MIRBuilder.buildInstr(SPIRV::OpAliasScopeListDeclINTEL).addDef(Ret);
229-
for (auto *Scope : ScopeList)
230-
MIB.addUse(Scope->getOperand(0).getReg());
231-
auto List = MIB.getInstr();
232-
AliasInstMDMap.insert(std::make_pair(AliasingListMD, List));
233-
return List;
234-
}
235-
236-
void buildMemAliasingOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
237-
uint32_t Dec, const MDNode *AliasingListMD) {
238-
MachineInstr *AliasList =
239-
getOrAddMemAliasingINTELInst(MIRBuilder, AliasingListMD);
240-
if (!AliasList)
241-
return;
242-
MIRBuilder.buildInstr(SPIRV::OpDecorate)
243-
.addUse(Reg)
244-
.addImm(Dec)
245-
.addUse(AliasList->getOperand(0).getReg());
246-
}
247-
248177
MachineBasicBlock::iterator getOpVariableMBBIt(MachineInstr &I) {
249178
MachineFunction *MF = I.getParent()->getParent();
250179
MachineBasicBlock *MBB = &MF->front();

‎llvm/lib/Target/SPIRV/SPIRVUtils.h‎

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -148,13 +148,8 @@ void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
148148
void buildOpSpirvDecorations(Register Reg, MachineIRBuilder &MIRBuilder,
149149
const MDNode *GVarMD);
150150

151-
// Add OpAliasDomainDeclINTEL, OpAliasScopeINTEL and OpAliasScopeListDeclINTEL
152-
// instructions.
153-
MachineInstr *getOrAddMemAliasingINTELInst(MachineIRBuilder &MIRBuilder,
154-
const MDNode *AliasingListMD);
155-
156-
void buildMemAliasingOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
157-
uint32_t Dec, const MDNode *GVarMD);
151+
//void buildMemAliasingOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
152+
// uint32_t Dec, const MDNode *GVarMD);
158153

159154
// Return a valid position for the OpVariable instruction inside a function,
160155
// i.e., at the beginning of the first block of the function.

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-barrier.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; The test checks if the backend won't crash
22

3-
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_memory_access_aliasing %s -o - | FileCheck %s
3+
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown -verify-machineinstrs --spirv-ext=+SPV_INTEL_memory_access_aliasing %s -o - | FileCheck %s
44

55
; CHECK: OpControlBarrier
66
; CHECK-NOT: MemoryAccessAliasingINTEL

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-empty-md.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
; Check aliasing information translation on load and store
55

6-
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_memory_access_aliasing %s -o - | FileCheck %s
6+
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown -verify-machineinstrs --spirv-ext=+SPV_INTEL_memory_access_aliasing %s -o - | FileCheck %s
77

88
; CHECK-NOT: MemoryAccessAliasingINTEL
99
; CHECK-NOT: SPV_INTEL_memory_access_aliasing

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store-atomic.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; Check aliasing information translation on atomic load and store
22

3-
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_memory_access_aliasing %s -o - | FileCheck %s
3+
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown -verify-machineinstrs --spirv-ext=+SPV_INTEL_memory_access_aliasing %s -o - | FileCheck %s
44

55
; CHECK: OpCapability MemoryAccessAliasingINTEL
66
; CHECK: OpExtension "SPV_INTEL_memory_access_aliasing"

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