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VyacheslavLevytskyyVyacheslavLevytskyy
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add a test case
1 parent 7080789 commit b76171b

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2 files changed

+37
-31
lines changed

2 files changed

+37
-31
lines changed

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1161,9 +1161,15 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
11611161

11621162
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
11631163
if (Call->isSpirvOp()) {
1164-
if (GroupBuiltin->NoGroupOperation)
1164+
if (GroupBuiltin->NoGroupOperation) {
1165+
SmallVector<uint32_t, 1> ImmArgs;
1166+
if (GroupBuiltin->Opcode ==
1167+
SPIRV::OpSubgroupMatrixMultiplyAccumulateINTEL &&
1168+
Call->Arguments.size() > 4)
1169+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[4], MRI));
11651170
return buildOpFromWrapper(MIRBuilder, GroupBuiltin->Opcode, Call,
1166-
GR->getSPIRVTypeID(Call->ReturnType));
1171+
GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
1172+
}
11671173

11681174
// Group Operation is a literal
11691175
Register GroupOpReg = Call->Arguments[1];

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroup_matrix_multiply_accumulate/subgroup_matrix_multiply_accumulate_generic.ll‎

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -131,35 +131,35 @@
131131
; CHECK: %[[#hM2:]] = OpFunctionParameter %[[#Vec2HalfTy]]
132132
; CHECK: %[[#hM4:]] = OpFunctionParameter %[[#Vec4HalfTy]]
133133
; CHECK: %[[#hM8:]] = OpFunctionParameter %[[#Vec8HalfTy]]
134-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#iM]] %[[#iM8]] %[[#iM]] 10
135-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#iM2]] %[[#iM8]] %[[#iM2]] 10
136-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#iM4]] %[[#iM8]] %[[#iM4]] 10
137-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#iM8]] %[[#iM8]] %[[#iM8]] 10
138-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#iM]] %[[#iM8]] %[[#fM]] 10
139-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#iM2]] %[[#iM8]] %[[#fM2]] 10
140-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#iM4]] %[[#iM8]] %[[#fM4]] 10
141-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#iM8]] %[[#iM8]] %[[#fM8]] 10
142-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#iM]] 10
143-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#iM2]] 10
144-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#iM4]] 10
145-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int32Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#iM8]] 10
146-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#fM]] 10
147-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#fM2]] 10
148-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#fM4]] 10
149-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#fM8]] 10
150-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#HalfTy]] %[[#Id1:]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#hM]] 10
151-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2HalfTy]] %[[#Id1:]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#hM2]] 10
152-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4HalfTy]] %[[#Id1:]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#hM4]] 10
153-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8HalfTy]] %[[#Id1:]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#hM8]] 10
154-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int16Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#sM]] 10
155-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int16Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#sM2]] 10
156-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int16Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#sM4]] 10
157-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int16Ty]] %[[#Id1:]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#sM8]] 10
158-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#fM]] %[[#fM8]] %[[#fM]] 10
159-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#fM2]] %[[#fM8]] %[[#fM2]] 10
160-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#fM4]] %[[#fM8]] %[[#fM4]] 10
161-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#fM8]] %[[#fM8]] %[[#fM8]] 10
162-
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Id1:]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#fM4]]
134+
; CHECK: %[[#]] = OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int32Ty]] %[[#Const42]] %[[#iM]] %[[#iM8]] %[[#iM]] 10
135+
; CHECK: %[[#]] = OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int32Ty]] %[[#Const42]] %[[#iM2]] %[[#iM8]] %[[#iM2]] 10
136+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int32Ty]] %[[#Const42]] %[[#iM4]] %[[#iM8]] %[[#iM4]] 10
137+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int32Ty]] %[[#Const42]] %[[#iM8]] %[[#iM8]] %[[#iM8]] 10
138+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Const42]] %[[#iM]] %[[#iM8]] %[[#fM]] 10
139+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Const42]] %[[#iM2]] %[[#iM8]] %[[#fM2]] 10
140+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#iM4]] %[[#iM8]] %[[#fM4]] 10
141+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Const42]] %[[#iM8]] %[[#iM8]] %[[#fM8]] 10
142+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int32Ty]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#iM]] 10
143+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int32Ty]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#iM2]] 10
144+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int32Ty]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#iM4]] 10
145+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int32Ty]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#iM8]] 10
146+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#fM]] 10
147+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#fM2]] 10
148+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#fM4]] 10
149+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#fM8]] 10
150+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#HalfTy]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#hM]] 10
151+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2HalfTy]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#hM2]] 10
152+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4HalfTy]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#hM4]] 10
153+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8HalfTy]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#hM8]] 10
154+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Int16Ty]] %[[#Const42]] %[[#sM]] %[[#iM8]] %[[#sM]] 10
155+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2Int16Ty]] %[[#Const42]] %[[#sM2]] %[[#iM8]] %[[#sM2]] 10
156+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4Int16Ty]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#sM4]] 10
157+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8Int16Ty]] %[[#Const42]] %[[#sM8]] %[[#iM8]] %[[#sM8]] 10
158+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#FloatTy]] %[[#Const42]] %[[#fM]] %[[#fM8]] %[[#fM]] 10
159+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec2FloatTy]] %[[#Const42]] %[[#fM2]] %[[#fM8]] %[[#fM2]] 10
160+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#fM4]] %[[#fM8]] %[[#fM4]] 10
161+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec8FloatTy]] %[[#Const42]] %[[#fM8]] %[[#fM8]] %[[#fM8]] 10
162+
; CHECK: OpSubgroupMatrixMultiplyAccumulateINTEL %[[#Vec4FloatTy]] %[[#Const42]] %[[#sM4]] %[[#iM8]] %[[#fM4]]
163163

164164
define spir_func void @foo(i32 %iM, <2 x i32> %iM2, <4 x i32> %iM4, <8 x i32> %iM8,
165165
i16 signext %sM, <2 x i16> %sM2, <4 x i16> %sM4, <8 x i16> %sM8,

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