Added tests.

Author: egorshamshura

llvm/test/Transforms/InstCombine/redundant-add-in-and.ll

@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i1 @addition_and_bitwise1(ptr %0) {
+; CHECK-LABEL: define i1 @addition_and_bitwise1(
+; CHECK-SAME: ptr [[TMP0:%.*]]) {
+; CHECK-NEXT:    [[V0:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    [[V1:%.*]] = load i32, ptr [[V0]], align 4
+; CHECK-NEXT:    [[V2:%.*]] = zext i32 [[V1]] to i64
+; CHECK-NEXT:    [[V3:%.*]] = ptrtoint ptr [[V0]] to i64
+; CHECK-NEXT:    [[V4:%.*]] = add i64 [[V2]], [[V3]]
+; CHECK-NEXT:    [[V5:%.*]] = and i64 [[V4]], 2
+; CHECK-NEXT:    [[V6:%.*]] = icmp eq i64 [[V5]], 0
+; CHECK-NEXT:    ret i1 [[V6]]
+;
+  %v0 = getelementptr inbounds nuw i8, ptr %0, i64 4
+  %v1 = load i32, ptr %v0, align 4
+  %v2 = zext i32 %v1 to i64
+  %v3 = ptrtoint ptr %v0 to i64
+  %v4 = add i64 %v2, %v3
+  %v5 = and i64 %v4, 2
+  %v6 = icmp eq i64 %v5, 0
+  ret i1 %v6
+}
+
+define i1 @addition_and_bitwise2(ptr %0) {
+; CHECK-LABEL: define i1 @addition_and_bitwise2(
+; CHECK-SAME: ptr [[TMP0:%.*]]) {
+; CHECK-NEXT:    [[V0:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    [[V1:%.*]] = load i32, ptr [[V0]], align 16
+; CHECK-NEXT:    [[V2:%.*]] = zext i32 [[V1]] to i64
+; CHECK-NEXT:    [[V3:%.*]] = ptrtoint ptr [[V0]] to i64
+; CHECK-NEXT:    [[V4:%.*]] = add i64 [[V2]], [[V3]]
+; CHECK-NEXT:    [[V5:%.*]] = and i64 [[V4]], 4
+; CHECK-NEXT:    [[V6:%.*]] = icmp eq i64 [[V5]], 0
+; CHECK-NEXT:    ret i1 [[V6]]
+;
+  %v0 = getelementptr inbounds nuw i8, ptr %0, i64 4
+  %v1 = load i32, ptr %v0, align 16
+  %v2 = zext i32 %v1 to i64
+  %v3 = ptrtoint ptr %v0 to i64
+  %v4 = add i64 %v2, %v3
+  %v5 = and i64 %v4, 4
+  %v6 = icmp eq i64 %v5, 0
+  ret i1 %v6
+}
+
+define i1 @addition_and_bitwise3(ptr %0) {
+; CHECK-LABEL: define i1 @addition_and_bitwise3(
+; CHECK-SAME: ptr [[TMP0:%.*]]) {
+; CHECK-NEXT:    [[V0:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT:    [[V1:%.*]] = load i32, ptr [[V0]], align 16
+; CHECK-NEXT:    [[V2:%.*]] = zext i32 [[V1]] to i64
+; CHECK-NEXT:    [[V3:%.*]] = ptrtoint ptr [[V0]] to i64
+; CHECK-NEXT:    [[V4:%.*]] = add i64 [[V3]], [[V2]]
+; CHECK-NEXT:    [[V5:%.*]] = and i64 [[V4]], 4
+; CHECK-NEXT:    [[V6:%.*]] = icmp eq i64 [[V5]], 0
+; CHECK-NEXT:    ret i1 [[V6]]
+;
+  %v0 = getelementptr inbounds nuw i8, ptr %0, i64 4
+  %v1 = load i32, ptr %v0, align 16
+  %v2 = zext i32 %v1 to i64
+  %v3 = ptrtoint ptr %v0 to i64
+  %v4 = add i64 %v3, %v2
+  %v5 = and i64 %v4, 4
+  %v6 = icmp eq i64 %v5, 0
+  ret i1 %v6
+}
+
+define i32 @test(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X]], 2
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %y_masked = and i32 %y, -4
+  %add = add i32 %x, %y_masked
+  %and = and i32 %add, 2
+  ret i32 %and
+}
+