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[Mips] Fix atomic min/max generate mips4 instructions when compiling for mips2 (#149983)
Fix #145411.
1 parent 56ebbeb commit b7f68cb

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2 files changed

+709
-25
lines changed

2 files changed

+709
-25
lines changed

‎llvm/lib/Target/Mips/MipsExpandPseudo.cpp‎

Lines changed: 188 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -432,23 +432,44 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
432432
Register OldVal = I->getOperand(6).getReg();
433433
Register BinOpRes = I->getOperand(7).getReg();
434434
Register StoreVal = I->getOperand(8).getReg();
435+
bool NoMovnInstr = (IsMin || IsMax) && !STI->hasMips4() && !STI->hasMips32();
435436

436437
const BasicBlock *LLVM_BB = BB.getBasicBlock();
437438
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
439+
MachineBasicBlock *loop1MBB;
440+
MachineBasicBlock *loop2MBB;
441+
if (NoMovnInstr) {
442+
loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
443+
loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
444+
}
438445
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
439446
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
440447
MachineFunction::iterator It = ++BB.getIterator();
441448
MF->insert(It, loopMBB);
449+
if (NoMovnInstr) {
450+
MF->insert(It, loop1MBB);
451+
MF->insert(It, loop2MBB);
452+
}
442453
MF->insert(It, sinkMBB);
443454
MF->insert(It, exitMBB);
444455

445456
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
446457
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
447458

448459
BB.addSuccessor(loopMBB, BranchProbability::getOne());
449-
loopMBB->addSuccessor(sinkMBB);
450-
loopMBB->addSuccessor(loopMBB);
460+
if (NoMovnInstr) {
461+
loopMBB->addSuccessor(loop1MBB);
462+
loopMBB->addSuccessor(loop2MBB);
463+
} else {
464+
loopMBB->addSuccessor(sinkMBB);
465+
loopMBB->addSuccessor(loopMBB);
466+
}
451467
loopMBB->normalizeSuccProbs();
468+
if (NoMovnInstr) {
469+
loop1MBB->addSuccessor(loop2MBB);
470+
loop2MBB->addSuccessor(loopMBB);
471+
loop2MBB->addSuccessor(exitMBB, BranchProbability::getOne());
472+
}
452473

453474
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
454475
if (IsNand) {
@@ -525,7 +546,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
525546
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
526547
.addReg(BinOpRes)
527548
.addReg(Scratch4);
528-
} else {
549+
} else if (STI->hasMips4() || STI->hasMips32()) {
529550
// max: move BinOpRes, StoreVal
530551
// movn BinOpRes, Incr, Scratch4, BinOpRes
531552
// min: move BinOpRes, StoreVal
@@ -537,12 +558,59 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
537558
.addReg(Incr)
538559
.addReg(Scratch4)
539560
.addReg(BinOpRes);
561+
} else {
562+
// if min:
563+
// loopMBB: move BinOpRes, StoreVal
564+
// beq Scratch4, 0, loop1MBB
565+
// j loop2MBB
566+
// loop1MBB: move BinOpRes, Incr
567+
// loop2MBB: and BinOpRes, BinOpRes, Mask
568+
// and StoreVal, OlddVal, Mask2
569+
// or StoreVal, StoreVal, BinOpRes
570+
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
571+
// beq StoreVal, zero, loopMBB
572+
//
573+
// if max:
574+
// loopMBB: move BinOpRes, Incr
575+
// beq Scratch4, 0, loop1MBB
576+
// j loop2MBB
577+
// loop1MBB: move BinOpRes, StoreVal
578+
// loop2MBB: and BinOpRes, BinOpRes, Mask
579+
// and StoreVal, OlddVal, Mask2
580+
// or StoreVal, StoreVal, BinOpRes
581+
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
582+
// beq StoreVal, zero, loopMBB
583+
if (IsMin) {
584+
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
585+
.addReg(StoreVal)
586+
.addReg(Mips::ZERO);
587+
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
588+
.addReg(Incr)
589+
.addReg(Mips::ZERO);
590+
} else {
591+
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
592+
.addReg(Incr)
593+
.addReg(Mips::ZERO);
594+
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
595+
.addReg(StoreVal)
596+
.addReg(Mips::ZERO);
597+
}
598+
BuildMI(loopMBB, DL, TII->get(BEQ))
599+
.addReg(Scratch4)
600+
.addReg(Mips::ZERO)
601+
.addMBB(loop1MBB);
602+
BuildMI(loopMBB, DL, TII->get(Mips::B)).addMBB(loop2MBB);
540603
}
541604

542605
// and BinOpRes, BinOpRes, Mask
543-
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
544-
.addReg(BinOpRes)
545-
.addReg(Mask);
606+
if (NoMovnInstr)
607+
BuildMI(loop2MBB, DL, TII->get(Mips::AND), BinOpRes)
608+
.addReg(BinOpRes)
609+
.addReg(Mask);
610+
else
611+
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
612+
.addReg(BinOpRes)
613+
.addReg(Mask);
546614

547615
} else if (!IsSwap) {
548616
// <binop> binopres, oldval, incr2
@@ -564,14 +632,37 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
564632
// or StoreVal, StoreVal, BinOpRes
565633
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
566634
// beq StoreVal, zero, loopMBB
567-
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
568-
.addReg(OldVal).addReg(Mask2);
569-
BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
570-
.addReg(StoreVal).addReg(BinOpRes);
571-
BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
572-
.addReg(StoreVal).addReg(Ptr).addImm(0);
573-
BuildMI(loopMBB, DL, TII->get(BEQ))
574-
.addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
635+
if (NoMovnInstr) {
636+
BuildMI(loop2MBB, DL, TII->get(Mips::AND), StoreVal)
637+
.addReg(OldVal)
638+
.addReg(Mask2);
639+
BuildMI(loop2MBB, DL, TII->get(Mips::OR), StoreVal)
640+
.addReg(StoreVal)
641+
.addReg(BinOpRes);
642+
BuildMI(loop2MBB, DL, TII->get(SC), StoreVal)
643+
.addReg(StoreVal)
644+
.addReg(Ptr)
645+
.addImm(0);
646+
BuildMI(loop2MBB, DL, TII->get(BEQ))
647+
.addReg(StoreVal)
648+
.addReg(Mips::ZERO)
649+
.addMBB(loopMBB);
650+
} else {
651+
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
652+
.addReg(OldVal)
653+
.addReg(Mask2);
654+
BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
655+
.addReg(StoreVal)
656+
.addReg(BinOpRes);
657+
BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
658+
.addReg(StoreVal)
659+
.addReg(Ptr)
660+
.addImm(0);
661+
BuildMI(loopMBB, DL, TII->get(BEQ))
662+
.addReg(StoreVal)
663+
.addReg(Mips::ZERO)
664+
.addMBB(loopMBB);
665+
}
575666

576667
// sinkMBB:
577668
// and maskedoldval1,oldval,mask
@@ -600,6 +691,10 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
600691

601692
LivePhysRegs LiveRegs;
602693
computeAndAddLiveIns(LiveRegs, *loopMBB);
694+
if (NoMovnInstr) {
695+
computeAndAddLiveIns(LiveRegs, *loop1MBB);
696+
computeAndAddLiveIns(LiveRegs, *loop2MBB);
697+
}
603698
computeAndAddLiveIns(LiveRegs, *sinkMBB);
604699
computeAndAddLiveIns(LiveRegs, *exitMBB);
605700

@@ -746,20 +841,41 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
746841
llvm_unreachable("Unknown pseudo atomic!");
747842
}
748843

844+
bool NoMovnInstr = (IsMin || IsMax) && !STI->hasMips4() && !STI->hasMips32();
749845
const BasicBlock *LLVM_BB = BB.getBasicBlock();
750846
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
847+
MachineBasicBlock *loop1MBB;
848+
MachineBasicBlock *loop2MBB;
849+
if (NoMovnInstr) {
850+
loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
851+
loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
852+
}
751853
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
752854
MachineFunction::iterator It = ++BB.getIterator();
753855
MF->insert(It, loopMBB);
856+
if (NoMovnInstr) {
857+
MF->insert(It, loop1MBB);
858+
MF->insert(It, loop2MBB);
859+
}
754860
MF->insert(It, exitMBB);
755861

756862
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
757863
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
758864

759865
BB.addSuccessor(loopMBB, BranchProbability::getOne());
760-
loopMBB->addSuccessor(exitMBB);
761-
loopMBB->addSuccessor(loopMBB);
866+
if (NoMovnInstr) {
867+
loopMBB->addSuccessor(loop1MBB);
868+
loopMBB->addSuccessor(loop2MBB);
869+
} else {
870+
loopMBB->addSuccessor(exitMBB);
871+
loopMBB->addSuccessor(loopMBB);
872+
}
762873
loopMBB->normalizeSuccProbs();
874+
if (NoMovnInstr) {
875+
loop1MBB->addSuccessor(loop2MBB);
876+
loop2MBB->addSuccessor(loopMBB);
877+
loop2MBB->addSuccessor(exitMBB, BranchProbability::getOne());
878+
}
763879

764880
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
765881
assert((OldVal != Ptr) && "Clobbered the wrong ptr reg!");
@@ -802,7 +918,7 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
802918
BuildMI(loopMBB, DL, TII->get(OR), Scratch)
803919
.addReg(Scratch)
804920
.addReg(Scratch2);
805-
} else {
921+
} else if (STI->hasMips4() || STI->hasMips32()) {
806922
// max: move Scratch, OldVal
807923
// movn Scratch, Incr, Scratch2, Scratch
808924
// min: move Scratch, OldVal
@@ -814,6 +930,38 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
814930
.addReg(Incr)
815931
.addReg(Scratch2)
816932
.addReg(Scratch);
933+
} else {
934+
// if min:
935+
// loopMBB: move Scratch, OldVal
936+
// beq Scratch2_32, 0, loop1MBB
937+
// j loop2MBB
938+
// loop1MBB: move Scratch, Incr
939+
// loop2MBB: sc $2, 0($4)
940+
// beqz $2, $BB0_1
941+
// nop
942+
//
943+
// if max:
944+
// loopMBB: move Scratch, Incr
945+
// beq Scratch2_32, 0, loop1MBB
946+
// j loop2MBB
947+
// loop1MBB: move Scratch, OldVal
948+
// loop2MBB: sc $2, 0($4)
949+
// beqz $2, $BB0_1
950+
// nop
951+
if (IsMin) {
952+
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(OldVal).addReg(ZERO);
953+
BuildMI(loop1MBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
954+
} else {
955+
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
956+
BuildMI(loop1MBB, DL, TII->get(OR), Scratch)
957+
.addReg(OldVal)
958+
.addReg(ZERO);
959+
}
960+
BuildMI(loopMBB, DL, TII->get(BEQ))
961+
.addReg(Scratch2_32)
962+
.addReg(ZERO)
963+
.addMBB(loop1MBB);
964+
BuildMI(loopMBB, DL, TII->get(Mips::B)).addMBB(loop2MBB);
817965
}
818966

819967
} else if (Opcode) {
@@ -829,20 +977,35 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
829977
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
830978
}
831979

832-
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
833-
.addReg(Scratch)
834-
.addReg(Ptr)
835-
.addImm(0);
836-
BuildMI(loopMBB, DL, TII->get(BEQ))
837-
.addReg(Scratch)
838-
.addReg(ZERO)
839-
.addMBB(loopMBB);
980+
if (NoMovnInstr) {
981+
BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
982+
.addReg(Scratch)
983+
.addReg(Ptr)
984+
.addImm(0);
985+
BuildMI(loop2MBB, DL, TII->get(BEQ))
986+
.addReg(Scratch)
987+
.addReg(ZERO)
988+
.addMBB(loopMBB);
989+
} else {
990+
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
991+
.addReg(Scratch)
992+
.addReg(Ptr)
993+
.addImm(0);
994+
BuildMI(loopMBB, DL, TII->get(BEQ))
995+
.addReg(Scratch)
996+
.addReg(ZERO)
997+
.addMBB(loopMBB);
998+
}
840999

8411000
NMBBI = BB.end();
8421001
I->eraseFromParent();
8431002

8441003
LivePhysRegs LiveRegs;
8451004
computeAndAddLiveIns(LiveRegs, *loopMBB);
1005+
if (!STI->hasMips4() && !STI->hasMips32()) {
1006+
computeAndAddLiveIns(LiveRegs, *loop1MBB);
1007+
computeAndAddLiveIns(LiveRegs, *loop2MBB);
1008+
}
8461009
computeAndAddLiveIns(LiveRegs, *exitMBB);
8471010

8481011
return true;

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