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paulwalker-armpaulwalker-arm
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Fix whitespace formating within unit tests.
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2 files changed

+47
-47
lines changed

2 files changed

+47
-47
lines changed

‎llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_n
1010
; CHECK-NEXT: uunpklo z1.d, z2.s
1111
; CHECK-NEXT: ret
1212
%retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
13-
ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval
13+
ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval
1414
}
1515

1616
define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv8f16(<vscale x 8 x half> %vec) {
@@ -22,7 +22,7 @@ define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_n
2222
; CHECK-NEXT: uunpklo z1.s, z2.h
2323
; CHECK-NEXT: ret
2424
%retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
25-
ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval
25+
ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval
2626
}
2727

2828
define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv16f16(<vscale x 16 x half> %vec) {
@@ -33,7 +33,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_n
3333
; CHECK-NEXT: mov z0.d, z2.d
3434
; CHECK-NEXT: ret
3535
%retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
36-
ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval
36+
ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval
3737
}
3838

3939
define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv4f32(<vscale x 4 x float> %vec) {
@@ -45,7 +45,7 @@ define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32
4545
; CHECK-NEXT: uunpklo z1.d, z2.s
4646
; CHECK-NEXT: ret
4747
%retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
48-
ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
48+
ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
4949
}
5050

5151
define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv8f32(<vscale x 8 x float> %vec) {
@@ -56,7 +56,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32
5656
; CHECK-NEXT: mov z0.d, z2.d
5757
; CHECK-NEXT: ret
5858
%retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
59-
ret {<vscale x 4 x float>, <vscale x 4 x float>} %retval
59+
ret {<vscale x 4 x float>, <vscale x 4 x float>} %retval
6060
}
6161

6262
define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv4f64(<vscale x 4 x double> %vec) {
@@ -67,7 +67,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f
6767
; CHECK-NEXT: mov z0.d, z2.d
6868
; CHECK-NEXT: ret
6969
%retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
70-
ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
70+
ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
7171
}
7272

7373
define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv4bf16(<vscale x 4 x bfloat> %vec) {
@@ -79,7 +79,7 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2b
7979
; CHECK-NEXT: uunpklo z1.d, z2.s
8080
; CHECK-NEXT: ret
8181
%retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)
82-
ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
82+
ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
8383
}
8484

8585
define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv8bf16(<vscale x 8 x bfloat> %vec) {
@@ -91,7 +91,7 @@ define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4b
9191
; CHECK-NEXT: uunpklo z1.s, z2.h
9292
; CHECK-NEXT: ret
9393
%retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)
94-
ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
94+
ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
9595
}
9696

9797
define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv16bf16(<vscale x 16 x bfloat> %vec) {
@@ -102,7 +102,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8b
102102
; CHECK-NEXT: mov z0.d, z2.d
103103
; CHECK-NEXT: ret
104104
%retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)
105-
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
105+
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
106106
}
107107

108108
; Integers
@@ -115,7 +115,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv
115115
; CHECK-NEXT: mov z0.d, z2.d
116116
; CHECK-NEXT: ret
117117
%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
118-
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
118+
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
119119
}
120120

121121
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv16i16(<vscale x 16 x i16> %vec) {
@@ -126,7 +126,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv
126126
; CHECK-NEXT: mov z0.d, z2.d
127127
; CHECK-NEXT: ret
128128
%retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
129-
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
129+
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
130130
}
131131

132132
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxvv8i32(<vscale x 8 x i32> %vec) {
@@ -137,7 +137,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv
137137
; CHECK-NEXT: mov z0.d, z2.d
138138
; CHECK-NEXT: ret
139139
%retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
140-
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval
140+
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval
141141
}
142142

143143
define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv4i64(<vscale x 4 x i64> %vec) {
@@ -148,7 +148,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv
148148
; CHECK-NEXT: mov z0.d, z2.d
149149
; CHECK-NEXT: ret
150150
%retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
151-
ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
151+
ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
152152
}
153153

154154
; Predicated
@@ -160,7 +160,7 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv
160160
; CHECK-NEXT: mov p0.b, p2.b
161161
; CHECK-NEXT: ret
162162
%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
163-
ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
163+
ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
164164
}
165165

166166
define {<vscale x 8 x i1>, <vscale x 8 x i1>} @vector_deinterleave_nxv8i1_nxv16i1(<vscale x 16 x i1> %vec) {
@@ -172,7 +172,7 @@ define {<vscale x 8 x i1>, <vscale x 8 x i1>} @vector_deinterleave_nxv8i1_nxv16i
172172
; CHECK-NEXT: punpklo p1.h, p2.b
173173
; CHECK-NEXT: ret
174174
%retval = call {<vscale x 8 x i1>, <vscale x 8 x i1>} @llvm.vector.deinterleave2.nxv16i1(<vscale x 16 x i1> %vec)
175-
ret {<vscale x 8 x i1>, <vscale x 8 x i1>} %retval
175+
ret {<vscale x 8 x i1>, <vscale x 8 x i1>} %retval
176176
}
177177

178178
define {<vscale x 4 x i1>, <vscale x 4 x i1>} @vector_deinterleave_nxv4i1_nxv8i1(<vscale x 8 x i1> %vec) {
@@ -184,7 +184,7 @@ define {<vscale x 4 x i1>, <vscale x 4 x i1>} @vector_deinterleave_nxv4i1_nxv8i1
184184
; CHECK-NEXT: punpklo p1.h, p2.b
185185
; CHECK-NEXT: ret
186186
%retval = call {<vscale x 4 x i1>, <vscale x 4 x i1>} @llvm.vector.deinterleave2.nxv8i1(<vscale x 8 x i1> %vec)
187-
ret {<vscale x 4 x i1>, <vscale x 4 x i1>} %retval
187+
ret {<vscale x 4 x i1>, <vscale x 4 x i1>} %retval
188188
}
189189

190190
define {<vscale x 2 x i1>, <vscale x 2 x i1>} @vector_deinterleave_nxv2i1_nxv4i1(<vscale x 4 x i1> %vec) {
@@ -196,7 +196,7 @@ define {<vscale x 2 x i1>, <vscale x 2 x i1>} @vector_deinterleave_nxv2i1_nxv4i1
196196
; CHECK-NEXT: punpklo p1.h, p2.b
197197
; CHECK-NEXT: ret
198198
%retval = call {<vscale x 2 x i1>, <vscale x 2 x i1>} @llvm.vector.deinterleave2.nxv4i1(<vscale x 4 x i1> %vec)
199-
ret {<vscale x 2 x i1>, <vscale x 2 x i1>} %retval
199+
ret {<vscale x 2 x i1>, <vscale x 2 x i1>} %retval
200200
}
201201

202202

@@ -213,11 +213,11 @@ define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv
213213
; CHECK-NEXT: mov z1.d, z4.d
214214
; CHECK-NEXT: mov z2.d, z6.d
215215
; CHECK-NEXT: ret
216-
%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
217-
ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
216+
%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
217+
ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
218218
}
219219

220-
define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
220+
define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
221221
; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
222222
; CHECK: // %bb.0:
223223
; CHECK-NEXT: uzp1 z24.d, z2.d, z3.d
@@ -236,8 +236,8 @@ define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nx
236236
; CHECK-NEXT: mov z5.d, z29.d
237237
; CHECK-NEXT: mov z6.d, z30.d
238238
; CHECK-NEXT: ret
239-
%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
240-
ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
239+
%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
240+
ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
241241
}
242242

243243

@@ -251,8 +251,8 @@ define {<vscale x 8 x i8>, <vscale x 8 x i8>} @vector_deinterleave_nxv8i8_nxv16i
251251
; CHECK-NEXT: uzp1 z0.h, z2.h, z1.h
252252
; CHECK-NEXT: uzp2 z1.h, z2.h, z1.h
253253
; CHECK-NEXT: ret
254-
%retval = call {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %vec)
255-
ret {<vscale x 8 x i8>, <vscale x 8 x i8>} %retval
254+
%retval = call {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %vec)
255+
ret {<vscale x 8 x i8>, <vscale x 8 x i8>} %retval
256256
}
257257

258258
define {<vscale x 4 x i16>, <vscale x 4 x i16>} @vector_deinterleave_nxv4i16_nxv8i16(<vscale x 8 x i16> %vec) {
@@ -263,8 +263,8 @@ define {<vscale x 4 x i16>, <vscale x 4 x i16>} @vector_deinterleave_nxv4i16_nxv
263263
; CHECK-NEXT: uzp1 z0.s, z2.s, z1.s
264264
; CHECK-NEXT: uzp2 z1.s, z2.s, z1.s
265265
; CHECK-NEXT: ret
266-
%retval = call {<vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.vector.deinterleave2.nxv8i16(<vscale x 8 x i16> %vec)
267-
ret {<vscale x 4 x i16>, <vscale x 4 x i16>} %retval
266+
%retval = call {<vscale x 4 x i16>, <vscale x 4 x i16>} @llvm.vector.deinterleave2.nxv8i16(<vscale x 8 x i16> %vec)
267+
ret {<vscale x 4 x i16>, <vscale x 4 x i16>} %retval
268268
}
269269

270270
define {<vscale x 2 x i32>, <vscale x 2 x i32>} @vector_deinterleave_nxv2i32_nxv4i32(<vscale x 4 x i32> %vec) {
@@ -275,8 +275,8 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @vector_deinterleave_nxv2i32_nxv
275275
; CHECK-NEXT: uzp1 z0.d, z2.d, z1.d
276276
; CHECK-NEXT: uzp2 z1.d, z2.d, z1.d
277277
; CHECK-NEXT: ret
278-
%retval = call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %vec)
279-
ret {<vscale x 2 x i32>, <vscale x 2 x i32>} %retval
278+
%retval = call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %vec)
279+
ret {<vscale x 2 x i32>, <vscale x 2 x i32>} %retval
280280
}
281281

282282

‎llvm/test/CodeGen/AArch64/sve-vector-interleave.ll‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ define <vscale x 4 x half> @interleave2_nxv4f16(<vscale x 2 x half> %vec0, <vsca
99
; CHECK-NEXT: uzp1 z0.s, z0.s, z2.s
1010
; CHECK-NEXT: ret
1111
%retval = call <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %vec0, <vscale x 2 x half> %vec1)
12-
ret <vscale x 4 x half> %retval
12+
ret <vscale x 4 x half> %retval
1313
}
1414

1515
define <vscale x 8 x half> @interleave2_nxv8f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1) {
@@ -20,7 +20,7 @@ define <vscale x 8 x half> @interleave2_nxv8f16(<vscale x 4 x half> %vec0, <vsca
2020
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
2121
; CHECK-NEXT: ret
2222
%retval = call <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1)
23-
ret <vscale x 8 x half> %retval
23+
ret <vscale x 8 x half> %retval
2424
}
2525

2626
define <vscale x 16 x half> @interleave2_nxv16f16(<vscale x 8 x half> %vec0, <vscale x 8 x half> %vec1) {
@@ -31,7 +31,7 @@ define <vscale x 16 x half> @interleave2_nxv16f16(<vscale x 8 x half> %vec0, <vs
3131
; CHECK-NEXT: mov z0.d, z2.d
3232
; CHECK-NEXT: ret
3333
%retval = call <vscale x 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half> %vec0, <vscale x 8 x half> %vec1)
34-
ret <vscale x 16 x half> %retval
34+
ret <vscale x 16 x half> %retval
3535
}
3636

3737
define <vscale x 4 x float> @interleave2_nxv4f32(<vscale x 2 x float> %vec0, <vscale x 2 x float> %vec1) {
@@ -42,7 +42,7 @@ define <vscale x 4 x float> @interleave2_nxv4f32(<vscale x 2 x float> %vec0, <vs
4242
; CHECK-NEXT: uzp1 z0.s, z0.s, z2.s
4343
; CHECK-NEXT: ret
4444
%retval = call <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> %vec0, <vscale x 2 x float> %vec1)
45-
ret <vscale x 4 x float> %retval
45+
ret <vscale x 4 x float> %retval
4646
}
4747

4848
define <vscale x 8 x float> @interleave2_nxv8f32(<vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1) {
@@ -53,7 +53,7 @@ define <vscale x 8 x float> @interleave2_nxv8f32(<vscale x 4 x float> %vec0, <vs
5353
; CHECK-NEXT: mov z0.d, z2.d
5454
; CHECK-NEXT: ret
5555
%retval = call <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1)
56-
ret <vscale x 8 x float> %retval
56+
ret <vscale x 8 x float> %retval
5757
}
5858

5959
define <vscale x 4 x double> @interleave2_nxv4f64(<vscale x 2 x double> %vec0, <vscale x 2 x double> %vec1) {
@@ -64,7 +64,7 @@ define <vscale x 4 x double> @interleave2_nxv4f64(<vscale x 2 x double> %vec0, <
6464
; CHECK-NEXT: mov z0.d, z2.d
6565
; CHECK-NEXT: ret
6666
%retval = call <vscale x 4 x double>@llvm.vector.interleave2.nxv4f64(<vscale x 2 x double> %vec0, <vscale x 2 x double> %vec1)
67-
ret <vscale x 4 x double> %retval
67+
ret <vscale x 4 x double> %retval
6868
}
6969

7070
define <vscale x 4 x bfloat> @interleave2_nxv4bf16(<vscale x 2 x bfloat> %vec0, <vscale x 2 x bfloat> %vec1) {
@@ -75,7 +75,7 @@ define <vscale x 4 x bfloat> @interleave2_nxv4bf16(<vscale x 2 x bfloat> %vec0,
7575
; CHECK-NEXT: uzp1 z0.s, z0.s, z2.s
7676
; CHECK-NEXT: ret
7777
%retval = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %vec0, <vscale x 2 x bfloat> %vec1)
78-
ret <vscale x 4 x bfloat> %retval
78+
ret <vscale x 4 x bfloat> %retval
7979
}
8080

8181
define <vscale x 8 x bfloat> @interleave2_nxv8bf16(<vscale x 4 x bfloat> %vec0, <vscale x 4 x bfloat> %vec1) {
@@ -86,7 +86,7 @@ define <vscale x 8 x bfloat> @interleave2_nxv8bf16(<vscale x 4 x bfloat> %vec0,
8686
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
8787
; CHECK-NEXT: ret
8888
%retval = call <vscale x 8 x bfloat> @llvm.vector.interleave2.nxv8bf16(<vscale x 4 x bfloat> %vec0, <vscale x 4 x bfloat> %vec1)
89-
ret <vscale x 8 x bfloat> %retval
89+
ret <vscale x 8 x bfloat> %retval
9090
}
9191

9292
define <vscale x 16 x bfloat> @interleave2_nxv16bf16(<vscale x 8 x bfloat> %vec0, <vscale x 8 x bfloat> %vec1) {
@@ -97,7 +97,7 @@ define <vscale x 16 x bfloat> @interleave2_nxv16bf16(<vscale x 8 x bfloat> %vec0
9797
; CHECK-NEXT: mov z0.d, z2.d
9898
; CHECK-NEXT: ret
9999
%retval = call <vscale x 16 x bfloat> @llvm.vector.interleave2.nxv16bf16(<vscale x 8 x bfloat> %vec0, <vscale x 8 x bfloat> %vec1)
100-
ret <vscale x 16 x bfloat> %retval
100+
ret <vscale x 16 x bfloat> %retval
101101
}
102102

103103
; Integers
@@ -109,8 +109,8 @@ define <vscale x 32 x i8> @interleave2_nxv32i8(<vscale x 16 x i8> %vec0, <vscale
109109
; CHECK-NEXT: zip2 z1.b, z0.b, z1.b
110110
; CHECK-NEXT: mov z0.d, z2.d
111111
; CHECK-NEXT: ret
112-
%retval = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %vec0, <vscale x 16 x i8> %vec1)
113-
ret <vscale x 32 x i8> %retval
112+
%retval = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %vec0, <vscale x 16 x i8> %vec1)
113+
ret <vscale x 32 x i8> %retval
114114
}
115115

116116
define <vscale x 16 x i16> @interleave2_nxv16i16(<vscale x 8 x i16> %vec0, <vscale x 8 x i16> %vec1) {
@@ -121,7 +121,7 @@ define <vscale x 16 x i16> @interleave2_nxv16i16(<vscale x 8 x i16> %vec0, <vsca
121121
; CHECK-NEXT: mov z0.d, z2.d
122122
; CHECK-NEXT: ret
123123
%retval = call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %vec0, <vscale x 8 x i16> %vec1)
124-
ret <vscale x 16 x i16> %retval
124+
ret <vscale x 16 x i16> %retval
125125
}
126126

127127
define <vscale x 8 x i32> @interleave2_nxv8i32(<vscale x 4 x i32> %vec0, <vscale x 4 x i32> %vec1) {
@@ -132,7 +132,7 @@ define <vscale x 8 x i32> @interleave2_nxv8i32(<vscale x 4 x i32> %vec0, <vscale
132132
; CHECK-NEXT: mov z0.d, z2.d
133133
; CHECK-NEXT: ret
134134
%retval = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %vec0, <vscale x 4 x i32> %vec1)
135-
ret <vscale x 8 x i32> %retval
135+
ret <vscale x 8 x i32> %retval
136136
}
137137

138138
define <vscale x 4 x i64> @interleave2_nxv4i64(<vscale x 2 x i64> %vec0, <vscale x 2 x i64> %vec1) {
@@ -143,7 +143,7 @@ define <vscale x 4 x i64> @interleave2_nxv4i64(<vscale x 2 x i64> %vec0, <vscale
143143
; CHECK-NEXT: mov z0.d, z2.d
144144
; CHECK-NEXT: ret
145145
%retval = call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %vec0, <vscale x 2 x i64> %vec1)
146-
ret <vscale x 4 x i64> %retval
146+
ret <vscale x 4 x i64> %retval
147147
}
148148

149149
; Predicated
@@ -155,8 +155,8 @@ define <vscale x 32 x i1> @interleave2_nxv32i1(<vscale x 16 x i1> %vec0, <vscale
155155
; CHECK-NEXT: zip2 p1.b, p0.b, p1.b
156156
; CHECK-NEXT: mov p0.b, p2.b
157157
; CHECK-NEXT: ret
158-
%retval = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %vec0, <vscale x 16 x i1> %vec1)
159-
ret <vscale x 32 x i1> %retval
158+
%retval = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %vec0, <vscale x 16 x i1> %vec1)
159+
ret <vscale x 32 x i1> %retval
160160
}
161161

162162
define <vscale x 16 x i1> @interleave2_nxv16i1(<vscale x 8 x i1> %vec0, <vscale x 8 x i1> %vec1) {
@@ -167,7 +167,7 @@ define <vscale x 16 x i1> @interleave2_nxv16i1(<vscale x 8 x i1> %vec0, <vscale
167167
; CHECK-NEXT: uzp1 p0.b, p0.b, p2.b
168168
; CHECK-NEXT: ret
169169
%retval = call <vscale x 16 x i1> @llvm.vector.interleave2.nxv16i1(<vscale x 8 x i1> %vec0, <vscale x 8 x i1> %vec1)
170-
ret <vscale x 16 x i1> %retval
170+
ret <vscale x 16 x i1> %retval
171171
}
172172

173173
define <vscale x 8 x i1> @interleave2_nxv8i1(<vscale x 4 x i1> %vec0, <vscale x 4 x i1> %vec1) {
@@ -178,7 +178,7 @@ define <vscale x 8 x i1> @interleave2_nxv8i1(<vscale x 4 x i1> %vec0, <vscale x
178178
; CHECK-NEXT: uzp1 p0.h, p0.h, p2.h
179179
; CHECK-NEXT: ret
180180
%retval = call <vscale x 8 x i1> @llvm.vector.interleave2.nxv8i1(<vscale x 4 x i1> %vec0, <vscale x 4 x i1> %vec1)
181-
ret <vscale x 8 x i1> %retval
181+
ret <vscale x 8 x i1> %retval
182182
}
183183

184184
define <vscale x 4 x i1> @interleave2_nxv4i1(<vscale x 2 x i1> %vec0, <vscale x 2 x i1> %vec1) {
@@ -189,7 +189,7 @@ define <vscale x 4 x i1> @interleave2_nxv4i1(<vscale x 2 x i1> %vec0, <vscale x
189189
; CHECK-NEXT: uzp1 p0.s, p0.s, p2.s
190190
; CHECK-NEXT: ret
191191
%retval = call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %vec0, <vscale x 2 x i1> %vec1)
192-
ret <vscale x 4 x i1> %retval
192+
ret <vscale x 4 x i1> %retval
193193
}
194194

195195
; Split illegal type size

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