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5 files changed

+38
-22
lines changed

‎llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@
88

99
#include "MCTargetDesc/PPCMCExpr.h"
1010
#include "MCTargetDesc/PPCMCTargetDesc.h"
11-
#include "PPCTargetStreamer.h"
1211
#include "PPCInstrInfo.h"
12+
#include "PPCTargetStreamer.h"
1313
#include "TargetInfo/PowerPCTargetInfo.h"
1414
#include "llvm/ADT/STLExtras.h"
1515
#include "llvm/ADT/Twine.h"
@@ -100,14 +100,10 @@ struct PPCOperand;
100100
class PPCAsmParser : public MCTargetAsmParser {
101101
bool IsPPC64;
102102

103-
bool UsesMemOp;
104-
105103
void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
106104

107105
bool isPPC64() const { return IsPPC64; }
108106

109-
bool usesMemOp() const { return UsesMemOp; }
110-
111107
MCRegister matchRegisterName(int64_t &IntVal);
112108

113109
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
@@ -135,6 +131,8 @@ class PPCAsmParser : public MCTargetAsmParser {
135131

136132
void processInstruction(MCInst &Inst, const OperandVector &Ops);
137133

134+
bool hasMemOp(const OperandVector &Ops);
135+
138136
/// @name Auto-generated Match Functions
139137
/// {
140138

@@ -151,7 +149,6 @@ class PPCAsmParser : public MCTargetAsmParser {
151149
// Check for 64-bit vs. 32-bit pointer mode.
152150
const Triple &TheTriple = STI.getTargetTriple();
153151
IsPPC64 = TheTriple.isPPC64();
154-
UsesMemOp = false;
155152
// Initialize the set of available features.
156153
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
157154
}
@@ -190,6 +187,7 @@ struct PPCOperand : public MCParsedAsmOperand {
190187

191188
struct ImmOp {
192189
int64_t Val;
190+
bool IsMemOp;
193191
};
194192

195193
struct ExprOp {
@@ -250,6 +248,11 @@ struct PPCOperand : public MCParsedAsmOperand {
250248
/// isPPC64 - True if this operand is for an instruction in 64-bit mode.
251249
bool isPPC64() const { return IsPPC64; }
252250

251+
/// isMemOp - True if this operand is a memory operand.
252+
bool isMemOp() const {
253+
return Kind == Immediate && Imm.IsMemOp;
254+
}
255+
253256
int64_t getImm() const {
254257
assert(Kind == Immediate && "Invalid access!");
255258
return Imm.Val;
@@ -702,9 +705,10 @@ struct PPCOperand : public MCParsedAsmOperand {
702705
}
703706

704707
static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
705-
bool IsPPC64) {
708+
bool IsPPC64, bool IsMemOp = false) {
706709
auto Op = std::make_unique<PPCOperand>(Immediate);
707710
Op->Imm.Val = Val;
711+
Op->Imm.IsMemOp = IsMemOp;
708712
Op->StartLoc = S;
709713
Op->EndLoc = E;
710714
Op->IsPPC64 = IsPPC64;
@@ -1263,10 +1267,11 @@ bool PPCAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
12631267
MCStreamer &Out, uint64_t &ErrorInfo,
12641268
bool MatchingInlineAsm) {
12651269
MCInst Inst;
1266-
const PPCInstrInfo *TII = static_cast<const PPCInstrInfo*>(&MII);
1270+
const PPCInstrInfo *TII = static_cast<const PPCInstrInfo *>(&MII);
1271+
12671272
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
12681273
case Match_Success:
1269-
if (usesMemOp() != TII->isMemOp(Inst.getOpcode()))
1274+
if (hasMemOp(Operands) != TII->isMemOp(Inst.getOpcode()))
12701275
return Error(IDLoc, "invalid operand for instruction");
12711276
// Post-process instructions (typically extended mnemonics)
12721277
processInstruction(Inst, Operands);
@@ -1603,7 +1608,6 @@ bool PPCAsmParser::parseOperand(OperandVector &Operands) {
16031608

16041609
// Otherwise, check for D-form memory operands
16051610
if (!TlsCall && parseOptionalToken(AsmToken::LParen)) {
1606-
UsesMemOp = true;
16071611
S = Parser.getTok().getLoc();
16081612

16091613
int64_t IntVal;
@@ -1626,7 +1630,7 @@ bool PPCAsmParser::parseOperand(OperandVector &Operands) {
16261630
E = Parser.getTok().getLoc();
16271631
if (parseToken(AsmToken::RParen, "missing ')'"))
16281632
return true;
1629-
Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1633+
Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64(), /*IsMemOp=*/true));
16301634
}
16311635

16321636
return false;
@@ -1635,7 +1639,6 @@ bool PPCAsmParser::parseOperand(OperandVector &Operands) {
16351639
/// Parse an instruction mnemonic followed by its operands.
16361640
bool PPCAsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
16371641
SMLoc NameLoc, OperandVector &Operands) {
1638-
UsesMemOp = false;
16391642
// The first operand is the token for the instruction name.
16401643
// If the next character is a '+' or '-', we need to add it to the
16411644
// instruction name, to match what TableGen is doing.
@@ -1915,3 +1918,12 @@ PPCAsmParser::applyModifierToExpr(const MCExpr *E,
19151918
return nullptr;
19161919
}
19171920
}
1921+
1922+
bool PPCAsmParser::hasMemOp(const OperandVector &Operands) {
1923+
for (const auto &Operand : Operands) {
1924+
const PPCOperand &Op = static_cast<const PPCOperand &>(*Operand);
1925+
if (Op.isMemOp())
1926+
return true;
1927+
}
1928+
return false;
1929+
}

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
218218
(ins (memrix $D, $RA):$src),
219219
"bctrl\n\tld 2, $src", IIC_BrB,
220220
[(PPCbctrl_load_toc iaddrX4:$src)]>,
221-
Requires<[In64BitMode]>, MemOp;
221+
Requires<[In64BitMode]>;
222222
}
223223

224224
let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
@@ -228,7 +228,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
228228
(ins (memrix $D, $RA):$src),
229229
"bctrl\n\tld 2, $src", IIC_BrB,
230230
[(PPCbctrl_load_toc_rm iaddrX4:$src)]>,
231-
Requires<[In64BitMode]>, MemOp;
231+
Requires<[In64BitMode]>;
232232
}
233233

234234
} // Interpretation64Bit
@@ -1457,7 +1457,7 @@ def LQ : DQForm_RTp5_RA17_MEM<56, 0,
14571457
"lq $RTp, $addr", IIC_LdStLQ,
14581458
[]>,
14591459
RegConstraint<"@earlyclobber $RTp">,
1460-
isPPC64, MemOp;
1460+
isPPC64;
14611461
// We don't really have LQX in the ISA, make a pseudo one so that we can
14621462
// handle x-form during isel. Make it pre-ra may expose
14631463
// oppotunities to some opts(CSE, LICM and etc.) for the result of adding

‎llvm/lib/Target/PowerPC/PPCInstrFormats.td‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,10 @@ class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
120120
let TSFlags{2} = PPC970_Cracked;
121121
let TSFlags{5-3} = PPC970_Unit;
122122

123+
// Indicate that this instruction uses a memory operand.
124+
bits<1> MemOp = 0;
125+
let TSFlags{10} = MemOp;
126+
123127
// Fields used for relation models.
124128
string BaseName = "";
125129
bit Interpretation64Bit = 0;
@@ -427,7 +431,7 @@ class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
427431
class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
428432
string asmstr, InstrItinClass itin,
429433
list<dag> pattern>
430-
: I<opcode, OOL, IOL, asmstr, itin> {
434+
: I<opcode, OOL, IOL, asmstr, itin>, MemOp {
431435
bits<5> RTp;
432436
bits<5> RA;
433437
bits<12> DQ;
@@ -1661,7 +1665,7 @@ class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
16611665
dag OOL, dag IOL, string asmstr,
16621666
InstrItinClass itin, list<dag> pattern>
16631667
: XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1664-
OOL, IOL, asmstr, itin, pattern> {
1668+
OOL, IOL, asmstr, itin, pattern>, MemOp {
16651669
let BO = bo;
16661670
let BI = bi;
16671671
let BH = 0;
@@ -1671,7 +1675,7 @@ class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo,
16711675
bits<5> bi, bit lk, bits<6> opcode2, dag OOL,
16721676
dag IOL, string asmstr, InstrItinClass itin,
16731677
list<dag> pattern>
1674-
: I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1678+
: I2<opcode1, opcode2, OOL, IOL, asmstr, itin>, MemOp {
16751679

16761680
bits<5> RST;
16771681
bits<5> RA;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1584,7 +1584,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
15841584
def BCTRL_LWZinto_toc:
15851585
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
15861586
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1587-
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>, MemOp;
1587+
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>;
15881588

15891589
}
15901590

@@ -1593,7 +1593,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
15931593
def BCTRL_LWZinto_toc_RM:
15941594
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
15951595
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1596-
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>, MemOp;
1596+
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>;
15971597

15981598
}
15991599

‎llvm/lib/Target/PowerPC/PPCInstrP10.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2518,10 +2518,10 @@ let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingI
25182518

25192519
def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI",
25202520
(ins g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>;
2521+
25212522
def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
25222523
(ins gprc_nor0:$RA, s34imm:$SI),
2523-
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemOp;
2524-
2524+
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemOp;
25252525
def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
25262526
(ins s34imm_pcrel:$SI),
25272527
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;

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