@@ -2853,38 +2853,43 @@ static SDValue lowerCvtRSIntrinsics(SDValue Op, SelectionDAG &DAG) {
28532853
28542854 unsigned IntrinsicID = N->getConstantOperandVal (0 );
28552855
2856- uint32_t CvtModeFlag = NVPTX::PTXCvtMode::CvtMode::RS;
2857-
28582856 // Extract the 4 float elements from the vector
28592857 SmallVector<SDValue, 6 > Ops;
28602858 for (unsigned i = 0 ; i < 4 ; ++i) {
28612859 Ops.push_back (DAG.getNode (ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32 , F32Vec,
28622860 DAG.getIntPtrConstant (i, DL)));
28632861 }
28642862
2865- auto OpSignature =
2866- [&]() -> std::pair<NVPTXISD::NodeType, MVT::SimpleValueType> {
2863+ using NVPTX::PTXCvtMode::CvtMode;
2864+
2865+ auto [OpCode, RetTy, CvtModeFlag] =
2866+ [&]() -> std::tuple<NVPTXISD::NodeType, MVT::SimpleValueType, uint32_t > {
28672867 switch (IntrinsicID) {
28682868 case Intrinsic::nvvm_f32x4_to_e4m3x4_rs_relu_satfinite:
2869- CvtModeFlag |= NVPTX::PTXCvtMode::CvtMode::RELU_FLAG;
2869+ return {NVPTXISD::CVT_E4M3X4_F32X4_RS_SF, MVT::v4i8,
2870+ CvtMode::RS | CvtMode::RELU_FLAG};
28702871 case Intrinsic::nvvm_f32x4_to_e4m3x4_rs_satfinite:
2871- return {NVPTXISD::CVT_E4M3X4_F32X4_RS_SF, MVT::v4i8};
2872+ return {NVPTXISD::CVT_E4M3X4_F32X4_RS_SF, MVT::v4i8, CvtMode::RS };
28722873 case Intrinsic::nvvm_f32x4_to_e5m2x4_rs_relu_satfinite:
2873- CvtModeFlag |= NVPTX::PTXCvtMode::CvtMode::RELU_FLAG;
2874+ return {NVPTXISD::CVT_E5M2X4_F32X4_RS_SF, MVT::v4i8,
2875+ CvtMode::RS | CvtMode::RELU_FLAG};
28742876 case Intrinsic::nvvm_f32x4_to_e5m2x4_rs_satfinite:
2875- return {NVPTXISD::CVT_E5M2X4_F32X4_RS_SF, MVT::v4i8};
2877+ return {NVPTXISD::CVT_E5M2X4_F32X4_RS_SF, MVT::v4i8, CvtMode::RS };
28762878 case Intrinsic::nvvm_f32x4_to_e2m3x4_rs_relu_satfinite:
2877- CvtModeFlag |= NVPTX::PTXCvtMode::CvtMode::RELU_FLAG;
2879+ return {NVPTXISD::CVT_E2M3X4_F32X4_RS_SF, MVT::v4i8,
2880+ CvtMode::RS | CvtMode::RELU_FLAG};
28782881 case Intrinsic::nvvm_f32x4_to_e2m3x4_rs_satfinite:
2879- return {NVPTXISD::CVT_E2M3X4_F32X4_RS_SF, MVT::v4i8};
2882+ return {NVPTXISD::CVT_E2M3X4_F32X4_RS_SF, MVT::v4i8, CvtMode::RS };
28802883 case Intrinsic::nvvm_f32x4_to_e3m2x4_rs_relu_satfinite:
2881- CvtModeFlag |= NVPTX::PTXCvtMode::CvtMode::RELU_FLAG;
2884+ return {NVPTXISD::CVT_E3M2X4_F32X4_RS_SF, MVT::v4i8,
2885+ CvtMode::RS | CvtMode::RELU_FLAG};
28822886 case Intrinsic::nvvm_f32x4_to_e3m2x4_rs_satfinite:
2883- return {NVPTXISD::CVT_E3M2X4_F32X4_RS_SF, MVT::v4i8};
2887+ return {NVPTXISD::CVT_E3M2X4_F32X4_RS_SF, MVT::v4i8, CvtMode::RS };
28842888 case Intrinsic::nvvm_f32x4_to_e2m1x4_rs_relu_satfinite:
2885- CvtModeFlag |= NVPTX::PTXCvtMode::CvtMode::RELU_FLAG;
2889+ return {NVPTXISD::CVT_E2M1X4_F32X4_RS_SF, MVT::i16 ,
2890+ CvtMode::RS | CvtMode::RELU_FLAG};
28862891 case Intrinsic::nvvm_f32x4_to_e2m1x4_rs_satfinite:
2887- return {NVPTXISD::CVT_E2M1X4_F32X4_RS_SF, MVT::i16 };
2892+ return {NVPTXISD::CVT_E2M1X4_F32X4_RS_SF, MVT::i16 , CvtMode::RS };
28882893 default :
28892894 llvm_unreachable (" unsupported/unhandled intrinsic" );
28902895 }
@@ -2893,7 +2898,7 @@ static SDValue lowerCvtRSIntrinsics(SDValue Op, SelectionDAG &DAG) {
28932898 Ops.push_back (RBits);
28942899 Ops.push_back (DAG.getConstant (CvtModeFlag, DL, MVT::i32 ));
28952900
2896- return DAG.getNode (OpSignature. first , DL, OpSignature. second , Ops);
2901+ return DAG.getNode (OpCode , DL, RetTy , Ops);
28972902}
28982903
28992904static SDValue lowerPrmtIntrinsic (SDValue Op, SelectionDAG &DAG) {
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