[LLVM][AArch64] Set hasAndNot() to true for scalable vectors.

NOTE: I've not added an SVE check because the use of scalable vectors
implies SVE or StreamingSVE must be available.

Author: paulwalker-arm

llvm/lib/Target/AArch64/AArch64ISelLowering.h

@@ -875,9 +875,10 @@ class AArch64TargetLowering : public TargetLowering {
     if (!VT.isVector())
       return hasAndNotCompare(Y);
 
-    TypeSize TS = VT.getSizeInBits();
-    // TODO: We should be able to use bic/bif too for SVE.
-    return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic'
+    if (VT.isScalableVector())
+      return true;
+
+    return VT.getFixedSizeInBits() >= 64; // vector 'bic'
   }
 
   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(

llvm/test/CodeGen/AArch64/sve2-bsl.ll

@@ -304,9 +304,7 @@ define <vscale x 2 x i64> @codegen_bsl2n_i64(<vscale x 2 x i64> %0, <vscale x 2
 define <vscale x 4 x i32> @bsl_combine_when_bic_available(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
 ; CHECK-LABEL: bsl_combine_when_bic_available:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    and z0.d, z0.d, z2.d
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
+; CHECK-NEXT:    bsl z0.d, z0.d, z1.d, z2.d
 ; CHECK-NEXT:    ret
 entry:
   %t1 = xor <vscale x 4 x i32> %a, %b

llvm/test/CodeGen/AArch64/vselect-constants.ll

@@ -369,10 +369,9 @@ define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
 define <vscale x 16 x i8> @signbit_mask_xor_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
 ; CHECK-LABEL: signbit_mask_xor_nxv16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    cmplt p0.b, p0/z, z0.b, #0
-; CHECK-NEXT:    eor z0.d, z0.d, z1.d
-; CHECK-NEXT:    mov z0.b, p0/m, #0 // =0x0
+; CHECK-NEXT:    eor z1.d, z0.d, z1.d
+; CHECK-NEXT:    asr z0.b, z0.b, #7
+; CHECK-NEXT:    bic z0.d, z1.d, z0.d
 ; CHECK-NEXT:    ret
   %cond = icmp slt <vscale x 16 x i8> %a, zeroinitializer
   %xor = xor <vscale x 16 x i8> %a, %b