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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt < %s -passes=always-inline -S | FileCheck %s |
| 3 | + |
| 4 | +define <2 x i64> @vpx_lpf_horizontal_4_sse2(<2 x i64> %0) { |
| 5 | +; CHECK-LABEL: define <2 x i64> @vpx_lpf_horizontal_4_sse2( |
| 6 | +; CHECK-SAME: <2 x i64> [[TMP0:%.*]]) { |
| 7 | +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> |
| 8 | +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP2]], <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> |
| 9 | +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64> |
| 10 | +; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <8 x i16> |
| 11 | +; CHECK-NEXT: [[TMP6:%.*]] = ashr <8 x i16> [[TMP5]], splat (i16 1) |
| 12 | +; CHECK-NEXT: ret <2 x i64> zeroinitializer |
| 13 | +; |
| 14 | + %2 = call fastcc <2 x i64> @_mm_unpackhi_epi8(<2 x i64> %0) |
| 15 | + %3 = call fastcc <2 x i64> @_mm_srai_epi16(<2 x i64> %2) |
| 16 | + ret <2 x i64> %3 |
| 17 | +} |
| 18 | + |
| 19 | +define fastcc <2 x i64> @_mm_unpackhi_epi8(<2 x i64> %0) #0 { |
| 20 | +; CHECK-LABEL: define fastcc <2 x i64> @_mm_unpackhi_epi8( |
| 21 | +; CHECK-SAME: <2 x i64> [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { |
| 22 | +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> |
| 23 | +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP2]], <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> |
| 24 | +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64> |
| 25 | +; CHECK-NEXT: ret <2 x i64> [[TMP4]] |
| 26 | +; |
| 27 | + %2 = bitcast <2 x i64> %0 to <16 x i8> |
| 28 | + %3 = shufflevector <16 x i8> %2, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> |
| 29 | + %4 = bitcast <16 x i8> %3 to <2 x i64> |
| 30 | + ret <2 x i64> %4 |
| 31 | +} |
| 32 | + |
| 33 | +define fastcc <2 x i64> @_mm_srai_epi16(<2 x i64> %0) #0 { |
| 34 | +; CHECK-LABEL: define fastcc <2 x i64> @_mm_srai_epi16( |
| 35 | +; CHECK-SAME: <2 x i64> [[TMP0:%.*]]) #[[ATTR0]] { |
| 36 | +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP0]] to <8 x i16> |
| 37 | +; CHECK-NEXT: [[TMP3:%.*]] = ashr <8 x i16> [[TMP2]], splat (i16 1) |
| 38 | +; CHECK-NEXT: ret <2 x i64> zeroinitializer |
| 39 | +; |
| 40 | + %2 = bitcast <2 x i64> %0 to <8 x i16> |
| 41 | + %3 = ashr <8 x i16> %2, splat (i16 1) |
| 42 | + ret <2 x i64> zeroinitializer |
| 43 | +} |
| 44 | + |
| 45 | +attributes #0 = { alwaysinline } |
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