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[LoongArch][NFC] Fix missing check prefixes in LSX build-vector.ll
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‎llvm/test/CodeGen/LoongArch/lsx/build-vector.ll‎

Lines changed: 129 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2-
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
3-
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
2+
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
3+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
44

55
define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind {
66
; CHECK-LABEL: buildvector_v16i8_splat:
@@ -42,6 +42,20 @@ entry:
4242
}
4343

4444
define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind {
45+
; LA32-LABEL: buildvector_v2i64_splat:
46+
; LA32: # %bb.0: # %entry
47+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
48+
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
49+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
50+
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3
51+
; LA32-NEXT: vst $vr0, $a0, 0
52+
; LA32-NEXT: ret
53+
;
54+
; LA64-LABEL: buildvector_v2i64_splat:
55+
; LA64: # %bb.0: # %entry
56+
; LA64-NEXT: vreplgr2vr.d $vr0, $a1
57+
; LA64-NEXT: vst $vr0, $a0, 0
58+
; LA64-NEXT: ret
4559
entry:
4660
%insert = insertelement <2 x i64> undef, i64 %a0, i8 0
4761
%splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -134,6 +148,19 @@ entry:
134148
}
135149

136150
define void @buildvector_v2f64_const_splat(ptr %dst) nounwind {
151+
; LA32-LABEL: buildvector_v2f64_const_splat:
152+
; LA32: # %bb.0: # %entry
153+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
154+
; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0)
155+
; LA32-NEXT: vst $vr0, $a0, 0
156+
; LA32-NEXT: ret
157+
;
158+
; LA64-LABEL: buildvector_v2f64_const_splat:
159+
; LA64: # %bb.0: # %entry
160+
; LA64-NEXT: lu52i.d $a1, $zero, 1023
161+
; LA64-NEXT: vreplgr2vr.d $vr0, $a1
162+
; LA64-NEXT: vst $vr0, $a0, 0
163+
; LA64-NEXT: ret
137164
entry:
138165
store <2 x double> <double 1.0, double 1.0>, ptr %dst
139166
ret void
@@ -212,6 +239,65 @@ entry:
212239
}
213240

214241
define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind {
242+
; LA32-LABEL: buildvector_v16i8:
243+
; LA32: # %bb.0: # %entry
244+
; LA32-NEXT: ld.b $t0, $sp, 32
245+
; LA32-NEXT: ld.b $t1, $sp, 28
246+
; LA32-NEXT: ld.b $t2, $sp, 24
247+
; LA32-NEXT: ld.b $t3, $sp, 20
248+
; LA32-NEXT: ld.b $t4, $sp, 16
249+
; LA32-NEXT: ld.b $t5, $sp, 12
250+
; LA32-NEXT: ld.b $t6, $sp, 8
251+
; LA32-NEXT: ld.b $t7, $sp, 4
252+
; LA32-NEXT: ld.b $t8, $sp, 0
253+
; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0
254+
; LA32-NEXT: vinsgr2vr.b $vr0, $a2, 1
255+
; LA32-NEXT: vinsgr2vr.b $vr0, $a3, 2
256+
; LA32-NEXT: vinsgr2vr.b $vr0, $a4, 3
257+
; LA32-NEXT: vinsgr2vr.b $vr0, $a5, 4
258+
; LA32-NEXT: vinsgr2vr.b $vr0, $a6, 5
259+
; LA32-NEXT: vinsgr2vr.b $vr0, $a7, 6
260+
; LA32-NEXT: vinsgr2vr.b $vr0, $t8, 7
261+
; LA32-NEXT: vinsgr2vr.b $vr0, $t7, 8
262+
; LA32-NEXT: vinsgr2vr.b $vr0, $t6, 9
263+
; LA32-NEXT: vinsgr2vr.b $vr0, $t5, 10
264+
; LA32-NEXT: vinsgr2vr.b $vr0, $t4, 11
265+
; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 12
266+
; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 13
267+
; LA32-NEXT: vinsgr2vr.b $vr0, $t1, 14
268+
; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 15
269+
; LA32-NEXT: vst $vr0, $a0, 0
270+
; LA32-NEXT: ret
271+
;
272+
; LA64-LABEL: buildvector_v16i8:
273+
; LA64: # %bb.0: # %entry
274+
; LA64-NEXT: ld.b $t0, $sp, 64
275+
; LA64-NEXT: ld.b $t1, $sp, 56
276+
; LA64-NEXT: ld.b $t2, $sp, 48
277+
; LA64-NEXT: ld.b $t3, $sp, 40
278+
; LA64-NEXT: ld.b $t4, $sp, 32
279+
; LA64-NEXT: ld.b $t5, $sp, 24
280+
; LA64-NEXT: ld.b $t6, $sp, 16
281+
; LA64-NEXT: ld.b $t7, $sp, 8
282+
; LA64-NEXT: ld.b $t8, $sp, 0
283+
; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0
284+
; LA64-NEXT: vinsgr2vr.b $vr0, $a2, 1
285+
; LA64-NEXT: vinsgr2vr.b $vr0, $a3, 2
286+
; LA64-NEXT: vinsgr2vr.b $vr0, $a4, 3
287+
; LA64-NEXT: vinsgr2vr.b $vr0, $a5, 4
288+
; LA64-NEXT: vinsgr2vr.b $vr0, $a6, 5
289+
; LA64-NEXT: vinsgr2vr.b $vr0, $a7, 6
290+
; LA64-NEXT: vinsgr2vr.b $vr0, $t8, 7
291+
; LA64-NEXT: vinsgr2vr.b $vr0, $t7, 8
292+
; LA64-NEXT: vinsgr2vr.b $vr0, $t6, 9
293+
; LA64-NEXT: vinsgr2vr.b $vr0, $t5, 10
294+
; LA64-NEXT: vinsgr2vr.b $vr0, $t4, 11
295+
; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 12
296+
; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 13
297+
; LA64-NEXT: vinsgr2vr.b $vr0, $t1, 14
298+
; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 15
299+
; LA64-NEXT: vst $vr0, $a0, 0
300+
; LA64-NEXT: ret
215301
entry:
216302
%ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0
217303
%ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1
@@ -621,6 +707,21 @@ entry:
621707
}
622708

623709
define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind {
710+
; LA32-LABEL: buildvector_v2i64:
711+
; LA32: # %bb.0: # %entry
712+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
713+
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
714+
; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 2
715+
; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 3
716+
; LA32-NEXT: vst $vr0, $a0, 0
717+
; LA32-NEXT: ret
718+
;
719+
; LA64-LABEL: buildvector_v2i64:
720+
; LA64: # %bb.0: # %entry
721+
; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0
722+
; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 1
723+
; LA64-NEXT: vst $vr0, $a0, 0
724+
; LA64-NEXT: ret
624725
entry:
625726
%ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
626727
%ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
@@ -629,6 +730,18 @@ entry:
629730
}
630731

631732
define void @buildvector_v2i64_partial(ptr %dst, i64 %a0) nounwind {
733+
; LA32-LABEL: buildvector_v2i64_partial:
734+
; LA32: # %bb.0: # %entry
735+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
736+
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
737+
; LA32-NEXT: vst $vr0, $a0, 0
738+
; LA32-NEXT: ret
739+
;
740+
; LA64-LABEL: buildvector_v2i64_partial:
741+
; LA64: # %bb.0: # %entry
742+
; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0
743+
; LA64-NEXT: vst $vr0, $a0, 0
744+
; LA64-NEXT: ret
632745
entry:
633746
%ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
634747
%ins1 = insertelement <2 x i64> %ins0, i64 undef, i32 1
@@ -637,6 +750,20 @@ entry:
637750
}
638751

639752
define void @buildvector_v2i64_with_constant(ptr %dst, i64 %a1) nounwind {
753+
; LA32-LABEL: buildvector_v2i64_with_constant:
754+
; LA32: # %bb.0: # %entry
755+
; LA32-NEXT: vrepli.b $vr0, 0
756+
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
757+
; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3
758+
; LA32-NEXT: vst $vr0, $a0, 0
759+
; LA32-NEXT: ret
760+
;
761+
; LA64-LABEL: buildvector_v2i64_with_constant:
762+
; LA64: # %bb.0: # %entry
763+
; LA64-NEXT: vrepli.b $vr0, 0
764+
; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 1
765+
; LA64-NEXT: vst $vr0, $a0, 0
766+
; LA64-NEXT: ret
640767
entry:
641768
%ins0 = insertelement <2 x i64> undef, i64 0, i32 0
642769
%ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1

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