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[NVPTX] Add support for PTX ISA v8.8
Support PTX version 8.8 (`-mattr=+ptx88`) from CUDA 12.9. The following new targets are also added: - Family-specific targets, which are compatible with all the subsequent architectures belonging to the same GPU family: sm_100f, sm_101f, sm_103f, sm_120f, sm_121f. - New archs: SM103 and SM121: sm_103, sm_103a, sm_121, sm_121a. Also, some things were reformatted.
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‎llvm/lib/Target/NVPTX/NVPTX.td‎

Lines changed: 48 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -36,17 +36,29 @@ class FeaturePTX<int version>:
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foreach sm = [20, 21, 30, 32, 35, 37, 50, 52, 53,
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60, 61, 62, 70, 72, 75, 80, 86, 87,
39-
89, 90, 100, 101, 120] in
39+
89, 90, 100, 101, 103, 120, 121] in
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def SM#sm: FeatureSM<""#sm, !mul(sm, 10)>;
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42-
def SM90a: FeatureSM<"90a", 901>;
42+
// Arch-specific targets. PTX for these is not compatible with any other
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// architectures.
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def SM90a : FeatureSM<"90a", 901>;
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def SM100a: FeatureSM<"100a", 1001>;
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def SM101a: FeatureSM<"101a", 1011>;
47+
def SM103a: FeatureSM<"103a", 1031>;
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def SM120a: FeatureSM<"120a", 1201>;
49+
def SM121a: FeatureSM<"121a", 1211>;
50+
51+
// Family-specific targets. PTX for these is compatible with all subsequent
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// targets in the same family.
53+
def SM100f: FeatureSM<"100f", 1002>;
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def SM101f: FeatureSM<"101f", 1012>;
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def SM103f: FeatureSM<"103f", 1032>;
56+
def SM120f: FeatureSM<"120f", 1202>;
57+
def SM121f: FeatureSM<"121f", 1212>;
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4759
foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65,
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70, 71, 72, 73, 74, 75, 76, 77, 78,
49-
80, 81, 82, 83, 84, 85, 86, 87] in
61+
80, 81, 82, 83, 84, 85, 86, 87, 88] in
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def PTX#version: FeaturePTX<version>;
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//===----------------------------------------------------------------------===//
@@ -56,33 +68,42 @@ foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65,
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
5870

59-
def : Proc<"sm_20", [SM20, PTX32]>;
60-
def : Proc<"sm_21", [SM21, PTX32]>;
61-
def : Proc<"sm_30", [SM30]>;
62-
def : Proc<"sm_32", [SM32, PTX40]>;
63-
def : Proc<"sm_35", [SM35, PTX32]>;
64-
def : Proc<"sm_37", [SM37, PTX41]>;
65-
def : Proc<"sm_50", [SM50, PTX40]>;
66-
def : Proc<"sm_52", [SM52, PTX41]>;
67-
def : Proc<"sm_53", [SM53, PTX42]>;
68-
def : Proc<"sm_60", [SM60, PTX50]>;
69-
def : Proc<"sm_61", [SM61, PTX50]>;
70-
def : Proc<"sm_62", [SM62, PTX50]>;
71-
def : Proc<"sm_70", [SM70, PTX60]>;
72-
def : Proc<"sm_72", [SM72, PTX61]>;
73-
def : Proc<"sm_75", [SM75, PTX63]>;
74-
def : Proc<"sm_80", [SM80, PTX70]>;
75-
def : Proc<"sm_86", [SM86, PTX71]>;
76-
def : Proc<"sm_87", [SM87, PTX74]>;
77-
def : Proc<"sm_89", [SM89, PTX78]>;
78-
def : Proc<"sm_90", [SM90, PTX78]>;
79-
def : Proc<"sm_90a", [SM90a, PTX80]>;
80-
def : Proc<"sm_100", [SM100, PTX86]>;
71+
def : Proc<"sm_20", [SM20, PTX32]>;
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def : Proc<"sm_21", [SM21, PTX32]>;
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def : Proc<"sm_30", [SM30]>;
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def : Proc<"sm_32", [SM32, PTX40]>;
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def : Proc<"sm_35", [SM35, PTX32]>;
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def : Proc<"sm_37", [SM37, PTX41]>;
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def : Proc<"sm_50", [SM50, PTX40]>;
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def : Proc<"sm_52", [SM52, PTX41]>;
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def : Proc<"sm_53", [SM53, PTX42]>;
80+
def : Proc<"sm_60", [SM60, PTX50]>;
81+
def : Proc<"sm_61", [SM61, PTX50]>;
82+
def : Proc<"sm_62", [SM62, PTX50]>;
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def : Proc<"sm_70", [SM70, PTX60]>;
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def : Proc<"sm_72", [SM72, PTX61]>;
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def : Proc<"sm_75", [SM75, PTX63]>;
86+
def : Proc<"sm_80", [SM80, PTX70]>;
87+
def : Proc<"sm_86", [SM86, PTX71]>;
88+
def : Proc<"sm_87", [SM87, PTX74]>;
89+
def : Proc<"sm_89", [SM89, PTX78]>;
90+
def : Proc<"sm_90", [SM90, PTX78]>;
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def : Proc<"sm_90a", [SM90a, PTX80]>;
92+
def : Proc<"sm_100", [SM100, PTX86]>;
8193
def : Proc<"sm_100a", [SM100a, PTX86]>;
82-
def : Proc<"sm_101", [SM101, PTX86]>;
94+
def : Proc<"sm_100f", [SM100f, PTX88]>;
95+
def : Proc<"sm_101", [SM101, PTX86]>;
8396
def : Proc<"sm_101a", [SM101a, PTX86]>;
84-
def : Proc<"sm_120", [SM120, PTX87]>;
97+
def : Proc<"sm_101f", [SM101f, PTX88]>;
98+
def : Proc<"sm_103", [SM103, PTX88]>;
99+
def : Proc<"sm_103a", [SM103a, PTX88]>;
100+
def : Proc<"sm_103f", [SM103f, PTX88]>;
101+
def : Proc<"sm_120", [SM120, PTX87]>;
85102
def : Proc<"sm_120a", [SM120a, PTX87]>;
103+
def : Proc<"sm_120f", [SM120f, PTX88]>;
104+
def : Proc<"sm_121", [SM121, PTX88]>;
105+
def : Proc<"sm_121a", [SM121a, PTX88]>;
106+
def : Proc<"sm_121f", [SM121f, PTX88]>;
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87108
def NVPTXInstrInfo : InstrInfo {
88109
}

‎llvm/test/CodeGen/NVPTX/sm-version.ll‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,10 +18,19 @@
1818
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_90a | FileCheck %s --check-prefix=SM90a
1919
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_100 | FileCheck %s --check-prefix=SM100
2020
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_100a | FileCheck %s --check-prefix=SM100a
21+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_100f | FileCheck %s --check-prefix=SM100f
2122
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_101 | FileCheck %s --check-prefix=SM101
2223
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_101a | FileCheck %s --check-prefix=SM101a
24+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_101f | FileCheck %s --check-prefix=SM101f
25+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_103 | FileCheck %s --check-prefix=SM103
26+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_103a | FileCheck %s --check-prefix=SM103a
27+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_103f | FileCheck %s --check-prefix=SM103f
2328
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_120 | FileCheck %s --check-prefix=SM120
2429
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_120a | FileCheck %s --check-prefix=SM120a
30+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_120f | FileCheck %s --check-prefix=SM120f
31+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_121 | FileCheck %s --check-prefix=SM121
32+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_121a | FileCheck %s --check-prefix=SM121a
33+
; RUN: llc < %s -mtriple=nvptx -mcpu=sm_121f | FileCheck %s --check-prefix=SM121f
2534

2635
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2736
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_21 | FileCheck %s --check-prefix=SM21
@@ -43,10 +52,19 @@
4352
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90a | FileCheck %s --check-prefix=SM90a
4453
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100 | FileCheck %s --check-prefix=SM100
4554
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100a | FileCheck %s --check-prefix=SM100a
55+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100f | FileCheck %s --check-prefix=SM100f
4656
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_101 | FileCheck %s --check-prefix=SM101
4757
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_101a | FileCheck %s --check-prefix=SM101a
58+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_101f | FileCheck %s --check-prefix=SM101f
59+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_103 | FileCheck %s --check-prefix=SM103
60+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_103a | FileCheck %s --check-prefix=SM103a
61+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_103f | FileCheck %s --check-prefix=SM103f
4862
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120 | FileCheck %s --check-prefix=SM120
4963
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120a | FileCheck %s --check-prefix=SM120a
64+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_120f | FileCheck %s --check-prefix=SM120f
65+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_121 | FileCheck %s --check-prefix=SM121
66+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_121a | FileCheck %s --check-prefix=SM121a
67+
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_121f | FileCheck %s --check-prefix=SM121f
5068

5169
; SM20: .version 3.2
5270
; SM21: .version 3.2
@@ -68,10 +86,19 @@
6886
; SM90a: .version 8.0
6987
; SM100: .version 8.6
7088
; SM100a: .version 8.6
89+
; SM100f: .version 8.8
7190
; SM101: .version 8.6
7291
; SM101a: .version 8.6
92+
; SM101f: .version 8.8
93+
; SM103: .version 8.8
94+
; SM103a: .version 8.8
95+
; SM103f: .version 8.8
7396
; SM120: .version 8.7
7497
; SM120a: .version 8.7
98+
; SM120f: .version 8.8
99+
; SM121: .version 8.8
100+
; SM121a: .version 8.8
101+
; SM121f: .version 8.8
75102

76103
; SM20: .target sm_20
77104
; SM21: .target sm_21
@@ -93,7 +120,16 @@
93120
; SM90a: .target sm_90a
94121
; SM100: .target sm_100
95122
; SM100a: .target sm_100a
123+
; SM100f: .target sm_100f
96124
; SM101: .target sm_101
97125
; SM101a: .target sm_101a
126+
; SM101f: .target sm_101f
127+
; SM103: .target sm_103
128+
; SM103a: .target sm_103a
129+
; SM103f: .target sm_103f
98130
; SM120: .target sm_120
99131
; SM120a: .target sm_120a
132+
; SM120f: .target sm_120f
133+
; SM121: .target sm_121
134+
; SM121a: .target sm_121a
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; SM121f: .target sm_121f

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