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1 parent b6b7f43 commit b9a662dCopy full SHA for b9a662d
llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -412,8 +412,8 @@ void ModuloScheduleExpander::generateExistingPhis(
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InitVal, NewReg);
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auto It = VRMap[CurStageNum].find(LoopVal);
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if (It != VRMap[CurStageNum].end()) {
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- llvm::Register &Reg = VRMap[CurStageNum][Def];
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- Reg = It->second;
+ llvm::Register Reg = It->second;
+ VRMap[CurStageNum][Def] = Reg;
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}
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// Adjust the number of Phis needed depending on the number of prologs left,
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