Rebase. Updates per latest review. Squash.

Author: JonPsson1

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -1230,7 +1230,7 @@ class GenericSchedulerBase : public MachineSchedStrategy {
 };
 
 // Utility functions used by heuristics in tryCandidate().
-unsigned computeRemLatency(SchedBoundary &CurrZone);  // XXX LLVM_ABI?
+LLVM_ABI unsigned computeRemLatency(SchedBoundary &CurrZone);
 LLVM_ABI bool tryLess(int TryVal, int CandVal,
                       GenericSchedulerBase::SchedCandidate &TryCand,
                       GenericSchedulerBase::SchedCandidate &Cand,

llvm/include/llvm/CodeGen/RegisterPressure.h

@@ -413,6 +413,8 @@ class RegPressureTracker {
   /// tracker before the first call to advance/recede.
   LLVM_ABI void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
 
+  bool isRegLive(Register Reg) const { return LiveRegs.contains(Reg).any(); }
+
   /// Get the MI position corresponding to this register pressure.
   MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
 

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -95,6 +95,8 @@ STATISTIC(NumOnly1PreRA,
           "Number of scheduling units chosen for Only1 heuristic pre-RA");
 STATISTIC(NumPhysRegPreRA,
           "Number of scheduling units chosen for PhysReg heuristic pre-RA");
+STATISTIC(NumLiveReducePreRA,
+          "Number of scheduling units chosen for LiveReduce heuristic pre-RA");
 STATISTIC(NumRegExcessPreRA,
           "Number of scheduling units chosen for RegExcess heuristic pre-RA");
 STATISTIC(NumRegCriticalPreRA,
@@ -140,6 +142,8 @@ STATISTIC(NumOnly1PostRA,
           "Number of scheduling units chosen for Only1 heuristic post-RA");
 STATISTIC(NumPhysRegPostRA,
           "Number of scheduling units chosen for PhysReg heuristic post-RA");
+STATISTIC(NumLiveReducePostRA,
+          "Number of scheduling units chosen for LiveReduce heuristic post-RA");
 STATISTIC(NumRegExcessPostRA,
           "Number of scheduling units chosen for RegExcess heuristic post-RA");
 STATISTIC(
@@ -3524,6 +3528,9 @@ static void tracePick(GenericSchedulerBase::CandReason Reason, bool IsTop,
     case GenericScheduler::PhysReg:
       NumPhysRegPostRA++;
       return;
+    case GenericScheduler::LivenessReduce:
+      NumLiveReducePostRA++;
+      return;
     case GenericScheduler::RegExcess:
       NumRegExcessPostRA++;
       return;
@@ -3583,6 +3590,9 @@ static void tracePick(GenericSchedulerBase::CandReason Reason, bool IsTop,
     case GenericScheduler::PhysReg:
       NumPhysRegPreRA++;
       return;
+    case GenericScheduler::LivenessReduce:
+      NumLiveReducePreRA++;
+      return;
     case GenericScheduler::RegExcess:
       NumRegExcessPreRA++;
       return;

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

@@ -2162,26 +2162,20 @@ bool SystemZInstrInfo::isLoadAndTestAsCmp(const MachineInstr &MI) const {
   return (MI.getOpcode() == SystemZ::LTEBR ||
           MI.getOpcode() == SystemZ::LTDBR ||
           MI.getOpcode() == SystemZ::LTXBR) &&
-    MI.getOperand(0).isDead();
+         MI.getOperand(0).isDead();
 }
 
 bool SystemZInstrInfo::isCompareZero(const MachineInstr &Compare) const {
   if (isLoadAndTestAsCmp(Compare))
     return true;
   return Compare.isCompare() && Compare.getNumExplicitOperands() == 2 &&
-    Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
+         Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
 }
 
-unsigned SystemZInstrInfo::
-getCompareSourceReg(const MachineInstr &Compare) const {
-  unsigned reg = 0;
-  if (Compare.isCompare())
-    reg = Compare.getOperand(0).getReg();
-  else if (isLoadAndTestAsCmp(Compare))
-    reg = Compare.getOperand(1).getReg();
-  assert(reg);
-
-  return reg;
+Register
+SystemZInstrInfo::getCompareSourceReg(const MachineInstr &Compare) const {
+  assert(isCompareZero(Compare) && "Expected a compare with 0.");
+  return Compare.getOperand(isLoadAndTestAsCmp(Compare) ? 1 : 0).getReg();
 }
 
 bool SystemZInstrInfo::

llvm/lib/Target/SystemZ/SystemZInstrInfo.h

@@ -365,7 +365,7 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
 
   // Return the source register of Compare, which is the unknown value
   // being tested.
-  unsigned getCompareSourceReg(const MachineInstr &Compare) const;
+  Register getCompareSourceReg(const MachineInstr &Compare) const;
 
   // Try to find all CC users of the compare instruction (MBBI) and update
   // all of them to maintain equivalent behavior after swapping the compare