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Pranav-TanejaPranav-Taneja
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[LiveRegUnits] Enhanced the register liveness check
Currently there's only a provision to check whether a register is contained in the LiveRegUnits BitVector. Introducing the method which is available in LivePhysRegs to check whether the register is not reserved as well. The naming convention has been retained like in LivePhysRegs.
1 parent be5b666 commit ba4a495

16 files changed

+67
-62
lines changed

‎llvm/include/llvm/CodeGen/LiveRegUnits.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -112,13 +112,13 @@ class LiveRegUnits {
112112
/// The regmask has the same format as the one in the RegMask machine operand.
113113
void addRegsInMask(const uint32_t *RegMask);
114114

115-
/// Returns true if no part of physical register \p Reg is live.
116-
bool available(MCPhysReg Reg) const {
117-
for (MCRegUnit Unit : TRI->regunits(Reg)) {
118-
if (Units.test(Unit))
119-
return false;
120-
}
121-
return true;
115+
/// Returns true if no part of physical register \p Reg is live or reserved.
116+
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
117+
118+
/// Returns true if any part of physical register \p Reg is live
119+
bool contains(MCPhysReg Reg) const {
120+
return llvm::any_of(TRI->regunits(Reg),
121+
[&](MCRegUnit Unit) { return Units.test(Unit); });
122122
}
123123

124124
/// Updates liveness when stepping backwards over the instruction \p MI.

‎llvm/include/llvm/CodeGen/MachineOutliner.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ struct Candidate {
156156
const TargetRegisterInfo &TRI) {
157157
if (!FromEndOfBlockToStartOfSeqWasSet)
158158
initFromEndOfBlockToStartOfSeq(TRI);
159-
return FromEndOfBlockToStartOfSeq.available(Reg);
159+
return !FromEndOfBlockToStartOfSeq.contains(Reg);
160160
}
161161

162162
/// \returns True if `isAvailableAcrossAndOutOfSeq` fails for any register
@@ -166,7 +166,7 @@ struct Candidate {
166166
if (!FromEndOfBlockToStartOfSeqWasSet)
167167
initFromEndOfBlockToStartOfSeq(TRI);
168168
return any_of(Regs, [&](Register Reg) {
169-
return !FromEndOfBlockToStartOfSeq.available(Reg);
169+
return FromEndOfBlockToStartOfSeq.contains(Reg);
170170
});
171171
}
172172

@@ -181,7 +181,7 @@ struct Candidate {
181181
bool isAvailableInsideSeq(Register Reg, const TargetRegisterInfo &TRI) {
182182
if (!InSeqWasSet)
183183
initInSeq(TRI);
184-
return InSeq.available(Reg);
184+
return !InSeq.contains(Reg);
185185
}
186186

187187
/// The number of instructions that would be saved by outlining every

‎llvm/lib/CodeGen/DeadMachineInstructionElim.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
7979
Register Reg = MO.getReg();
8080
if (Reg.isPhysical()) {
8181
// Don't delete live physreg defs, or any reserved register defs.
82-
if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
82+
if (!LivePhysRegs.available(*MRI, Reg))
8383
return false;
8484
} else {
8585
if (MO.isDead()) {

‎llvm/lib/CodeGen/LiveRegUnits.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,11 @@ void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) {
4141
}
4242
}
4343

44+
bool LiveRegUnits::available(const MachineRegisterInfo &MRI,
45+
MCPhysReg Reg) const {
46+
return !MRI.isReserved(Reg) && !contains(Reg);
47+
}
48+
4449
void LiveRegUnits::stepBackward(const MachineInstr &MI) {
4550
// Remove defined registers and regmask kills from the set.
4651
for (const MachineOperand &MOP : MI.operands()) {

‎llvm/lib/CodeGen/MachineSink.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1627,7 +1627,7 @@ static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB, unsigned Reg,
16271627
const TargetRegisterInfo *TRI) {
16281628
LiveRegUnits LiveInRegUnits(*TRI);
16291629
LiveInRegUnits.addLiveIns(MBB);
1630-
return !LiveInRegUnits.available(Reg);
1630+
return LiveInRegUnits.contains(Reg);
16311631
}
16321632

16331633
static MachineBasicBlock *
@@ -1680,7 +1680,7 @@ static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB,
16801680
for (auto U : UsedOpsInCopy) {
16811681
MachineOperand &MO = MI->getOperand(U);
16821682
Register SrcReg = MO.getReg();
1683-
if (!UsedRegUnits.available(SrcReg)) {
1683+
if (UsedRegUnits.contains(SrcReg)) {
16841684
MachineBasicBlock::iterator NI = std::next(MI->getIterator());
16851685
for (MachineInstr &UI : make_range(NI, CurBB.end())) {
16861686
if (UI.killsRegister(SrcReg, TRI)) {
@@ -1725,7 +1725,7 @@ static bool hasRegisterDependency(MachineInstr *MI,
17251725
if (!Reg)
17261726
continue;
17271727
if (MO.isDef()) {
1728-
if (!ModifiedRegUnits.available(Reg) || !UsedRegUnits.available(Reg)) {
1728+
if (ModifiedRegUnits.contains(Reg) || UsedRegUnits.contains(Reg)) {
17291729
HasRegDependency = true;
17301730
break;
17311731
}
@@ -1736,7 +1736,7 @@ static bool hasRegisterDependency(MachineInstr *MI,
17361736
// it's not perfectly clear if skipping the internal read is safe in all
17371737
// other targets.
17381738
} else if (MO.isUse()) {
1739-
if (!ModifiedRegUnits.available(Reg)) {
1739+
if (ModifiedRegUnits.contains(Reg)) {
17401740
HasRegDependency = true;
17411741
break;
17421742
}

‎llvm/lib/CodeGen/RegisterScavenging.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ void RegScavenger::backward() {
109109
bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {
110110
if (isReserved(Reg))
111111
return includeReserved;
112-
return !LiveUnits.available(Reg);
112+
return LiveUnits.contains(Reg);
113113
}
114114

115115
Register RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
@@ -164,8 +164,8 @@ findSurvivorBackwards(const MachineRegisterInfo &MRI,
164164
if (I == To) {
165165
// See if one of the registers in RC wasn't used so far.
166166
for (MCPhysReg Reg : AllocationOrder) {
167-
if (!MRI.isReserved(Reg) && Used.available(Reg) &&
168-
LiveOut.available(Reg))
167+
if (!MRI.isReserved(Reg) && !Used.contains(Reg) &&
168+
!LiveOut.contains(Reg))
169169
return std::make_pair(Reg, MBB.end());
170170
}
171171
// Otherwise we will continue up to InstrLimit instructions to find
@@ -186,10 +186,10 @@ findSurvivorBackwards(const MachineRegisterInfo &MRI,
186186
MI.getFlag(MachineInstr::FrameSetup))
187187
break;
188188

189-
if (Survivor == 0 || !Used.available(Survivor)) {
189+
if (Survivor == 0 || Used.contains(Survivor)) {
190190
MCPhysReg AvilableReg = 0;
191191
for (MCPhysReg Reg : AllocationOrder) {
192-
if (!MRI.isReserved(Reg) && Used.available(Reg)) {
192+
if (Used.available(MRI, Reg)) {
193193
AvilableReg = Reg;
194194
break;
195195
}

‎llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -518,7 +518,7 @@ int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
518518
unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass;
519519
auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
520520
for (auto Reg : Ord) {
521-
if (!Units.available(Reg))
521+
if (Units.contains(Reg))
522522
continue;
523523
if (C == getColor(Reg))
524524
return Reg;

‎llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -748,7 +748,7 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) {
748748
}
749749

750750
for (unsigned ScratchReg : AArch64::GPR64RegClass) {
751-
if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))
751+
if (!LR.available(MRI, ScratchReg))
752752
continue;
753753

754754
LoadInfo NewLdI(LdI);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7838,8 +7838,8 @@ AArch64InstrInfo::getOutlinableRanges(MachineBasicBlock &MBB,
78387838
// where these registers are dead. We will only outline from those ranges.
78397839
LiveRegUnits LRU(getRegisterInfo());
78407840
auto AreAllUnsafeRegsDead = [&LRU]() {
7841-
return LRU.available(AArch64::W16) && LRU.available(AArch64::W17) &&
7842-
LRU.available(AArch64::NZCV);
7841+
return !LRU.contains(AArch64::W16) && !LRU.contains(AArch64::W17) &&
7842+
!LRU.contains(AArch64::NZCV);
78437843
};
78447844

78457845
// We need to know if LR is live across an outlining boundary later on in
@@ -7909,7 +7909,7 @@ AArch64InstrInfo::getOutlinableRanges(MachineBasicBlock &MBB,
79097909
CreateNewRangeStartingAt(MI.getIterator());
79107910
continue;
79117911
}
7912-
LRAvailableEverywhere &= LRU.available(AArch64::LR);
7912+
LRAvailableEverywhere &= !LRU.contains(AArch64::LR);
79137913
RangeBegin = MI.getIterator();
79147914
++RangeLen;
79157915
}

‎llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1265,7 +1265,7 @@ bool AArch64LoadStoreOpt::findMatchingStore(
12651265
BaseReg == AArch64InstrInfo::getLdStBaseOp(MI).getReg() &&
12661266
AArch64InstrInfo::getLdStOffsetOp(MI).isImm() &&
12671267
isLdOffsetInRangeOfSt(LoadMI, MI, TII) &&
1268-
ModifiedRegUnits.available(getLdStRegOp(MI).getReg())) {
1268+
!ModifiedRegUnits.contains(getLdStRegOp(MI).getReg())) {
12691269
StoreI = MBBI;
12701270
return true;
12711271
}
@@ -1278,7 +1278,7 @@ bool AArch64LoadStoreOpt::findMatchingStore(
12781278

12791279
// Otherwise, if the base register is modified, we have no match, so
12801280
// return early.
1281-
if (!ModifiedRegUnits.available(BaseReg))
1281+
if (ModifiedRegUnits.contains(BaseReg))
12821282
return false;
12831283

12841284
// If we encounter a store aliased with the load, return early.
@@ -1510,7 +1510,7 @@ static std::optional<MCPhysReg> tryToFindRegisterToRename(
15101510

15111511
auto *RegClass = TRI->getMinimalPhysRegClass(Reg);
15121512
for (const MCPhysReg &PR : *RegClass) {
1513-
if (DefinedInBB.available(PR) && UsedInBetween.available(PR) &&
1513+
if (!DefinedInBB.contains(PR) && !UsedInBetween.contains(PR) &&
15141514
!RegInfo.isReserved(PR) && !AnySubOrSuperRegCalleePreserved(PR) &&
15151515
CanBeUsedForAllClasses(PR)) {
15161516
DefinedInBB.addReg(PR);
@@ -1615,9 +1615,9 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
16151615
// can't be paired: bail and keep looking.
16161616
if (IsPreLdSt) {
16171617
bool IsOutOfBounds = MIOffset != TII->getMemScale(MI);
1618-
bool IsBaseRegUsed = !UsedRegUnits.available(
1618+
bool IsBaseRegUsed = UsedRegUnits.contains(
16191619
AArch64InstrInfo::getLdStBaseOp(MI).getReg());
1620-
bool IsBaseRegModified = !ModifiedRegUnits.available(
1620+
bool IsBaseRegModified = ModifiedRegUnits.contains(
16211621
AArch64InstrInfo::getLdStBaseOp(MI).getReg());
16221622
// If the stored value and the address of the second instruction is
16231623
// the same, it needs to be using the updated register and therefore
@@ -1694,16 +1694,16 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
16941694
// ldr x2 [x3]
16951695
// ldr x4 [x2, #8],
16961696
// the first and third ldr cannot be converted to ldp x1, x4, [x2]
1697-
if (!ModifiedRegUnits.available(BaseReg))
1697+
if (ModifiedRegUnits.contains(BaseReg))
16981698
return E;
16991699

17001700
// If the Rt of the second instruction was not modified or used between
17011701
// the two instructions and none of the instructions between the second
17021702
// and first alias with the second, we can combine the second into the
17031703
// first.
1704-
if (ModifiedRegUnits.available(getLdStRegOp(MI).getReg()) &&
1704+
if (!ModifiedRegUnits.contains(getLdStRegOp(MI).getReg()) &&
17051705
!(MI.mayLoad() &&
1706-
!UsedRegUnits.available(getLdStRegOp(MI).getReg())) &&
1706+
UsedRegUnits.contains(getLdStRegOp(MI).getReg())) &&
17071707
!mayAlias(MI, MemInsns, AA)) {
17081708

17091709
Flags.setMergeForward(false);
@@ -1716,10 +1716,10 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
17161716
// first and the second alias with the first, we can combine the first
17171717
// into the second.
17181718
if (!(MayLoad &&
1719-
!UsedRegUnits.available(getLdStRegOp(FirstMI).getReg())) &&
1719+
UsedRegUnits.contains(getLdStRegOp(FirstMI).getReg())) &&
17201720
!mayAlias(FirstMI, MemInsns, AA)) {
17211721

1722-
if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg())) {
1722+
if (!ModifiedRegUnits.contains(getLdStRegOp(FirstMI).getReg())) {
17231723
Flags.setMergeForward(true);
17241724
Flags.clearRenameReg();
17251725
return MBBI;
@@ -1761,7 +1761,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
17611761

17621762
// Otherwise, if the base register is modified, we have no match, so
17631763
// return early.
1764-
if (!ModifiedRegUnits.available(BaseReg))
1764+
if (ModifiedRegUnits.contains(BaseReg))
17651765
return E;
17661766

17671767
// Update list of instructions that read/write memory.
@@ -1987,8 +1987,8 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
19871987
// return early.
19881988
// If we are optimizing SP, do not allow instructions that may load or store
19891989
// in between the load and the optimized value update.
1990-
if (!ModifiedRegUnits.available(BaseReg) ||
1991-
!UsedRegUnits.available(BaseReg) ||
1990+
if (ModifiedRegUnits.contains(BaseReg) ||
1991+
UsedRegUnits.contains(BaseReg) ||
19921992
(BaseRegSP && MBBI->mayLoadOrStore()))
19931993
return E;
19941994
}
@@ -2062,8 +2062,8 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
20622062

20632063
// Otherwise, if the base register is used or modified, we have no match, so
20642064
// return early.
2065-
if (!ModifiedRegUnits.available(BaseReg) ||
2066-
!UsedRegUnits.available(BaseReg))
2065+
if (ModifiedRegUnits.contains(BaseReg) ||
2066+
UsedRegUnits.contains(BaseReg))
20672067
return E;
20682068
// Keep track if we have a memory access before an SP pre-increment, in this
20692069
// case we need to validate later that the update amount respects the red

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